DSPIC33FJ64MC204-I/ML Microchip Technology, DSPIC33FJ64MC204-I/ML Datasheet

IC DSPIC MCU/DSP 64K 44-QFN

DSPIC33FJ64MC204-I/ML

Manufacturer Part Number
DSPIC33FJ64MC204-I/ML
Description
IC DSPIC MCU/DSP 64K 44-QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ64MC204-I/ML

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
44-QFN
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164336 - MODULE SOCKET FOR PM3 28/44QFNDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04 and
dsPIC33FJ128MCX02/X04
Data Sheet
High-Performance,
16-bit Digital Signal Controllers
© 2011 Microchip Technology Inc.
DS70291E

Related parts for DSPIC33FJ64MC204-I/ML

DSPIC33FJ64MC204-I/ML Summary of contents

Page 1

... Microchip Technology Inc. High-Performance, 16-bit Digital Signal Controllers Data Sheet DS70291E ...

Page 2

... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA: - Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing) • Most peripherals support DMA © 2011 Microchip Technology Inc. dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04 Timers/Capture/Compare/PWM: • Timer/Counters five 16-bit timers: ...

Page 4

... Center-Aligned mode • 2-Quadrature Encoder Interface module: - Phase A, Phase B, and index pulse input - 16-bit up/down position counter - Count direction status - Position Measurement (x2 and x4) mode - Programmable digital noise filters on inputs - Alternate 16-bit Timer/Counter mode - Interrupt on position counter rollover/underflow © 2011 Microchip Technology Inc. ...

Page 5

... Supports 16 address lines • Programmable Cyclic Redundancy Check (CRC): - Programmable bit length for the CRC generator polynomial (up to 16-bit length) - 8-deep, 16-bit or 16-deep, 8-bit FIFO for data input © 2011 Microchip Technology Inc. Packaging: • 28-pin SDIP/SOIC/QFN-S • 44-pin TQFP/QFN Note: See ...

Page 6

... Note 1: RAM size is inclusive of 2 Kbytes of DMA RAM for all devices except dsPIC33FJ32MC302/304, which include 1 Kbyte of DMA RAM. 2: Only four out of five timers are remappable. 3: Only PWM fault pins are remappable. ...

Page 7

... AN4/C1IN-/RP2 /CN6/RB2 (1) AN5/C1IN+/RP3 /CN7/RB3 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/PMA0/RA3 Note 1: The RPx pins can be used by any remappable peripheral. See 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V © 2011 Microchip Technology Inc. MCLR PWM1L1/RP15 ...

Page 8

... CAP 27 7 dsPIC33FJ64MC804 dsPIC33FJ128MC804 (1) RP25 29 5 (1) RP24 30 4 PWM2L1/RP23 31 3 PWM2H1/RP22 32 2 SDA1/RP9 33 1 Table 1 in this section for the list of available peripherals. = Pins are tolerant (1) /CN13/PMRD/RB13 (1) /CN14/PMD0/RB12 (1) /CN15/PMD1/RB11 (1) /CN16/PMD2/RB10 /CN19/PMA6/RC9 /CN20/PMA5/RC8 (1) /CN17/PMA0/RC7 (1) /CN18/PMA1/RC6 (1) /CN21/PMD3/RB9 externally. SS © 2011 Microchip Technology Inc. ...

Page 9

... The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V © 2011 Microchip Technology Inc. PWM1L2/RP13 11 23 PWM1H2/RP12 24 10 PGEC2/PWM1L3/RP11 25 9 PGED2/PWM1H3/RP10 26 8 dsPIC33FJ32MC304 V CAP 27 7 dsPIC33FJ64MC204 (1) RP25 29 dsPIC33FJ128MC204 5 (1) RP24 30 4 PWM2L1/RP23 31 3 PWM2H1/RP2 32 ...

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... PGEC2/PWM1L3/RP11 8 26 PGED2/EMCD2/PWM1H3/RP10 CAP dsPIC33FJ64MC804 dsPIC33FJ128MC804 (1) 5 RP25 /CN19/PMA6/RC9 29 ( RP24 /CN20/PMA5/RC8 3 31 PWM2L1/RP23 2 32 PWM2H1/RP22 1 33 SDA1/RP9 Table 1 in this section for the list of available peripherals. = Pins are tolerant (1) /CN13/PMRD/RB13 (1) /CN14/PMD0/RB12 (1) /CN15/PMD1/RB11 (1) /CN16/PMD2/RB10 (1) /CN17/PMA0/RC7 (1) /CN18/PMA1/RC6 (1) /CN21/PMD3/RB9 © 2011 Microchip Technology Inc. ...

Page 11

... Note 1: The RPx pins can be used by any remappable peripheral. See © 2011 Microchip Technology Inc. PWM1L2/RP13 PWM1H2/RP12 25 PGEC2/PWM1L3/RP11 9 26 PGED2/EMCD2/PWM1H3/RP10 8 dsPIC33FJ32MC304 CAP dsPIC33FJ64MC204 SS (1) RP25 /CN19/PMA6/RC9 29 5 dsPIC33FJ128MC204 (1) RP24 /CN20/PMA5/RC8 PWM2L1/RP23 32 2 PWM2H1/RP22 33 SDA1/RP9 1 Table 1 in this section for the list of available peripherals. ...

Page 12

... High Temperature Electrical Characteristics ............................................................................................................................ 397 33.0 Packaging Information.............................................................................................................................................................. 407 Appendix A: Revision History............................................................................................................................................................. 417 Index ................................................................................................................................................................................................. 427 The Microchip Web Site ..................................................................................................................................................................... 433 Customer Change Notification Service .............................................................................................................................................. 433 Customer Support .............................................................................................................................................................................. 433 Reader Response .............................................................................................................................................................................. 434 Product Identification System............................................................................................................................................................. 435 DS70291E-page 12 © 2011 Microchip Technology Inc. ...

Page 13

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com © 2011 Microchip Technology Inc. to receive the most current information on all of our products. DS70291E-page 13 ...

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... AND dsPIC33FJ128MCX02/X04 NOTES: DS70291E-page 14 © 2011 Microchip Technology Inc. ...

Page 15

... Refer to Section 4.0 “Memory Organization” this data sheet for device-specific register and bit information. © 2011 Microchip Technology Inc. This document contains device specific information for the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/ X04 and dsPIC33FJ128MCX02/X04 Digital Signal Controller (DSC) Devices. The dsPIC33F devices ...

Page 16

... Divide Support MCLR OC/ Timers UART1, 2 ADC1 PWM1-4 1-5 IC1 QEI1, 2 CNx I2C1 PORTA DMA RAM PORTB 16 DMA Controller PORTC Remappable Pins 16-bit ALU 16 PWM 2 Ch PWM 6 Ch “Pin Diagrams” for the specific pins and features © 2011 Microchip Technology Inc. ...

Page 17

... ST ASDA1 I/O ST Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select © 2011 Microchip Technology Inc. PPS Description No Analog input channels. No External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...

Page 18

... DAC1 Negative Output. No DAC1 Positive Output. No DAC1 Output indicating middle point value (typically 1.65V). No DAC2 Negative Output. No DAC2 Positive Output. No DAC2 Output indicating middle point value (typically 1.65V). Analog = Analog input O = Output TTL = TTL input buffer P = Power I = Input © 2011 Microchip Technology Inc. ...

Page 19

... Analog REF Analog REF Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select © 2011 Microchip Technology Inc. PPS Description Yes PWM1 Fault A input. No PWM1 Low output 1 No PWM1 High output 1 No PWM1 Low output 2 ...

Page 20

... AND dsPIC33FJ128MCX02/X04 NOTES: DS70291E-page 20 © 2011 Microchip Technology Inc. ...

Page 21

... ADC module is implemented Note: The AV and connected independent of the ADC voltage reference source. © 2011 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • ...

Page 22

... Ensure that the MCLR pin V and V specifications are met MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V and V specifications are met © 2011 Microchip Technology Inc. is ...

Page 23

... REAL ICE™ In-Circuit Emulator User’s Guide” DS51616 ® • “Using MPLAB REAL ICE™” (poster) DS51749 © 2011 Microchip Technology Inc. 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Configuration” ...

Page 24

... DS70291E-page 24 2.9 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect 10k resistor between V and the unused pin. © 2011 Microchip Technology Inc. SS ...

Page 25

... Each of the working registers can serve as a data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls. © 2011 Microchip Technology Inc. There are dsPIC33FJ32MC302/304, and dsPIC33FJ128MCX02/X04 devices: MCU and DSP ...

Page 26

... The divide operation can be interrupted during any of those 19 cycles without loss of data. A 40-bit barrel shifter is used to perform 16-bit left or right shift in a single cycle. The barrel shifter can be used by both MCU and DSP instructions. © 2011 Microchip Technology Inc. ...

Page 27

... PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data Latch 24 Instruction Decode and Control Control Signals to Various Blocks © 2011 Microchip Technology Inc. Y Data Bus X Data Bus Data Latch Data Latch PCL X RAM Y RAM Address Address Loop Latch Control ...

Page 28

... CORCON DC IPL2 IPL1 IPL0 SRL PUSH.S Shadow DO Shadow Legend Working Registers Stack Pointer Limit Register AD15 AD0 Program Counter REPEAT Loop Counter DO Loop Counter DO Loop Start Address DO Loop End Address Core Configuration Register Z C STATUS Register © 2011 Microchip Technology Inc. ...

Page 29

... Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when the NSTDIS bit (INTCON1<15> This bit can be read or cleared (not set). Clearing this bit clears SA and SB. © 2011 Microchip Technology Inc. R/C-0 R-0 (1) (1) SB ...

Page 30

... Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when the NSTDIS bit (INTCON1<15> This bit can be read or cleared (not set). Clearing this bit clears SA and SB. DS70291E-page 30 (2) © 2011 Microchip Technology Inc. ...

Page 31

... Program space visible in data space 0 = Program space not visible in data space Note 1: This bit is always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2011 Microchip Technology Inc. R/W-0 R/W-0 R-0 (1) US ...

Page 32

... Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops Note 1: This bit is always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70291E-page 32 © 2011 Microchip Technology Inc. ...

Page 33

... The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. © 2011 Microchip Technology Inc. 3.7 DSP Engine The DSP engine consists of a high-speed 17-bit x ...

Page 34

... AND dsPIC33FJ128MCX02/X04 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70291E-page 34 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2011 Microchip Technology Inc. ...

Page 35

... In the case of subtraction, the Carry/Borrow input is active-low and the other input is complemented © 2011 Microchip Technology Inc. The adder/subtracter generates Overflow Status bits, SA/SB and OA/OB, which are latched and reflected in the STATUS register: • ...

Page 36

... Section 3.7.3.2 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. © 2011 Microchip Technology Inc. saturation (see ...

Page 37

... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2011 Microchip Technology Inc. 3.7.4 BARREL SHIFTER The barrel shifter can perform up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...

Page 38

... AND dsPIC33FJ128MCX02/X04 NOTES: DS70291E-page 38 © 2011 Microchip Technology Inc. ...

Page 39

... Unimplemented (Read ‘0’s) Reserved Device Configuration Registers Reserved DEVID (2) Reserved Note: Memory areas are not shown to scale. © 2011 Microchip Technology Inc. 4.1 Program Address Space The program dsPIC33FJ32MC302/304, and dsPIC33FJ128MCX02/X04 and instructions. The space is addressable by a 24-bit family ...

Page 40

... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Table”. least significant word Instruction Width dsPIC33FJ64MCX02/X04 Section 7.1 “Interrupt Vector PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2011 Microchip Technology Inc. ...

Page 41

... Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2011 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code ...

Page 42

... SFR Space 0x07FF 0x0801 X Data RAM (X) 0x0FFF 0x1001 Y Data RAM (Y) 0x13FF 0x1401 DMA RAM 0x17FF 0x1801 0x8001 X Data Unimplemented (X) LSb Address 0x0000 0x07FE 0x0800 6 Kbyte 0x0FFE Near 0x1000 Data Space 0x13FE 0x1400 0x17FE 0x1800 0x8000 0xFFFE © 2011 Microchip Technology Inc. ...

Page 43

... Kbyte 0x17FF 0x1801 SRAM Space 0x1FFF 0x2001 0x27FF 0x2801 0x8001 Optionally Mapped into Program Memory 0xFFFF © 2011 Microchip Technology Inc. LSb 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x17FE 0x1800 Y Data RAM (Y) 0x1FFE 0x2000 ...

Page 44

... Program Memory 0xFFFF DS70291E-page 44 LSb Address 16 bits MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x1FFE 0x27FE 0x2800 Y Data RAM (Y) 0x3FFE 0x4000 DMA RAM 0x47FE 0x4800 0x8000 X Data Unimplemented (X) 0xFFFE 8 Kbyte Near Data Space © 2011 Microchip Technology Inc. ...

Page 45

... All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. © 2011 Microchip Technology Inc. 4.2.6 DMA RAM Every dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/ ...

Page 46

TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...

Page 47

TABLE 4-1: CPU CORE REGISTERS MAP (CONTINUED) SFR SFR Name Bit 15 Bit 14 Bit 13 Addr XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN DISICNT 0052 — — Legend unknown value on Reset, — ...

Page 48

... CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU1 CNPU2 006A — CN30PUE CN29PUE — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 AND dsPIC33FJ32MC304 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr ...

Page 49

TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF AD1IF U1TXIF IFS1 0086 ...

Page 50

TABLE 4-5: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...

Page 51

TABLE 4-7: OUTPUT COMPARE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr OC1RS 0180 OC1R 0182 OC1CON 0184 OCSIDL — — — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS 018C ...

Page 52

TABLE 4-9: 2-OUTPUT PWM2 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P2TCON 05C0 PTEN — PTSIDL P2TMR 05C2 PTDIR P2TPER 05C4 — P2SECMP 05C6 SEVTDIR PWM2CON1 05C8 — — — PWM2CON2 05CA — — ...

Page 53

TABLE 4-12: I2C1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — I2CSIDL ...

Page 54

TABLE 4-15: SPI1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr SPI1STAT 0240 SPIEN — SPISIDL SPI1CON1 0242 — — — DISSCK SPI1CON2 0244 FRMEN SPIFSD FRMPOL SPI1BUF 0248 Legend unknown value ...

Page 55

... TABLE 4-18: ADC1 REGISTER MAP FOR dsPIC33FJ64MC204/804, dsPIC33FJ128MC204/804 AND dsPIC33FJ32MC304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 AD1CON1 0320 ADON — ADSIDL ADDMABM AD1CON2 0322 VCFG<2:0> — AD1CON3 0324 ADRC — — AD1CHS123 0326 — — — — AD1CHS0 ...

Page 56

TABLE 4-20: DMA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA0CON 0380 CHEN SIZE DIR HALF DMA0REQ 0382 FORCE — — — DMA0STA 0384 DMA0STB 0386 DMA0PAD 0388 DMA0CNT 038A — — — — ...

Page 57

TABLE 4-20: DMA REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA5PAD 03C4 DMA5CNT 03C6 — — — — DMA6CON 03C8 CHEN SIZE DIR HALF DMA6REQ 03CA FORCE — — — DMA6STA 03CC DMA6STB ...

Page 58

TABLE 4-21: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = (FOR dsPIC33FJ128MC802/804 AND dsPIC33FJ64MC802/804) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1CTRL1 0400 — — CSIDL ABAT C1CTRL2 0402 — — — C1VEC 0404 — ...

Page 59

TABLE 4-23: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (FOR dsPIC33FJ128MC802/804 AND dsPIC33FJ64MC802/804) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0400- 041E C1BUFPNT1 0420 F3BP<3:0> C1BUFPNT2 0422 F7BP<3:0> C1BUFPNT3 0424 F11BP<3:0> C1BUFPNT4 0426 F15BP<3:0> C1RXM0SID 0430 ...

Page 60

TABLE 4-23: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (FOR dsPIC33FJ128MC802/804 AND dsPIC33FJ64MC802/804) (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1RXF11EID 046E C1RXF12SID 0470 C1RXF12EID 0472 C1RXF13SID 0474 C1RXF13EID 0476 C1RXF14SID 0478 C1RXF14EID 047A C1RXF15SID ...

Page 61

TABLE 4-24: PERIPHERAL PIN SELECT INPUT REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RPINR0 0680 — — — RPINR1 0682 — — — — RPINR3 0686 — — — RPINR4 0688 — — — ...

Page 62

... RPOR7 06CE — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-26: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 AND dsPIC33FJ32MC304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RPOR0 06C0 — ...

Page 63

... PMSTAT 060E IBF IBOV — — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-28: PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 AND dsPIC33FJ32MC304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 PMCON 0600 PMPEN — ...

Page 64

TABLE 4-29: REAL-TIME CLOCK AND CALENDAR REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 ALRMVAL 0620 ALCFGRPT 0622 ALRMEN CHIME RTCVAL 0624 RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC PADCFG1 02FC — — — Legend unknown ...

Page 65

... LATB12 ODCB 02CE — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-35: PORTC REGISTER MAP FOR dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 AND dsPIC33FJ32MC304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 — — — ...

Page 66

... TABLE 4-37: SECURITY REGISTER MAP FOR dsPIC33FJ128MC204/804 AND dsPIC33FJ64MC204/804 ONLY File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 BSRAM 0750 — — — — SSRAM 0752 — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. ...

Page 67

... Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2011 Microchip Technology Inc. 4.2.8 DATA RAM PROTECTION FEATURE The dsPIC33F product family supports Data RAM protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security ...

Page 68

... ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. MAC INSTRUCTIONS Register Indirect with Register Offset Addressing mode is available only for W9 (in X space) and W11 (in Y space). OTHER INSTRUCTIONS © 2011 Microchip Technology Inc. ...

Page 69

... Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2011 Microchip Technology Inc. The length of a circular buffer is not directly specified determined by corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes) ...

Page 70

... If Bit-Reversed Addressing has already been enabled by setting the BREN bit (XBREV<15>), a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. N bytes, should not be enabled © 2011 Microchip Technology Inc. ...

Page 71

... TABLE 4-41: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address © 2011 Microchip Technology Inc. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer Bit-Reversed Address Decimal Decimal ...

Page 72

... TBLPAG<7:0> 0xxx xxxx xxxx xxxx xxxx xxxx TBLPAG<7:0> 1xxx xxxx xxxx xxxx xxxx xxxx PSVPAG<7:0> xxxx xxxx © 2011 Microchip Technology Inc. show how the program EA is <14:1> <0> 0 xxxx xxx0 Data EA<15:0> Data EA<15:0> (1) Data EA<14:0> xxx xxxx xxxx xxxx ...

Page 73

... Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. © 2011 Microchip Technology Inc. Program Counter 0 23 bits ...

Page 74

... TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 0x800000 Only read operations are shown; write operations are also valid in the user memory area. Section 5.0 “Flash © 2011 Microchip Technology Inc. ...

Page 75

... PSVPAG is mapped into the upper half of the data memory space... © 2011 Microchip Technology Inc. 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...

Page 76

... AND dsPIC33FJ128MCX02/X04 NOTES: DS70291E-page 76 © 2011 Microchip Technology Inc. ...

Page 77

... Program Counter Using 1/0 Table Instruction User/Configuration Space Select © 2011 Microchip Technology Inc. programming clock and programming data (one of the alternate programming pin pairs: PGECx/PGEDx), and three other lines for power (V Master Clear (MCLR). This allows customers to and manufacture boards with unprogrammed devices and ...

Page 78

... Section 5.3 “Programming Operations” further details. 31-12). )% Equation 5-2. MINIMUM ROW WRITE TIME 11064 Cycles = × × 0.05 1 0.00375 – Equation 5-3. MAXIMUM ROW WRITE TIME 11064 Cycles = × × 0.05 – 1 0.00375 – (Register 5-1) (Register 5- write-only for © 2011 Microchip Technology Inc. ...

Page 79

... Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2011 Microchip Technology Inc. (1) U-0 U-0 — — (1) U-0 R/W-0 — ...

Page 80

... NVMKEY<7:0>: Key Register (write-only) bits DS70291E-page 80 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 81

... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2011 Microchip Technology Inc. 4. Write the first 64 instructions from data RAM into the program memory buffers (see 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit ...

Page 82

... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted © 2011 Microchip Technology Inc. ...

Page 83

... Regulator V DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2011 Microchip Technology Inc. A simplified block diagram of the Reset module is shown in Figure Any active source of reset will make the SYSRST signal active. On system Reset, some of the registers and associated with the CPU and peripherals are forced to ...

Page 84

... SWDTEN bit setting. DS70291E-page 84 (1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) U-0 R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 85

... All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2011 Microchip Technology Inc. (1) (CONTINUED) DS70291E-page 85 ...

Page 86

... PLL Lock Time Total Delay — T OSCD LOCK OSCD LOCK — OSCD OST — OSCD OST — — LOCK OSCD OST T LOCK LOCK OSCD OST T LOCK T T LOCK LOCK — OSCD OST — T OSCD = 102.4 μs for a OST © 2011 Microchip Technology Inc. ...

Page 87

... GOTO instruction at the reset address, which redirects program execution to the appropriate start-up routine. 6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay T © 2011 Microchip Technology Inc. Vbor V BOR ...

Page 88

... The BOR crosses DD has elapsed. The BOR ensures the voltage regulator output ) is programmed by PWRT Reset Timer Value Select Section 28.0 “Special Features” initiated each time V BOR PWRT trip point BOR © 2011 Microchip Technology Inc. bits DD ...

Page 89

... Reset state. This Reset state will not re- initialize the clock. The clock source in effect prior to the RESET instruction will remain. SYSRST is released at the next instruction cycle, and the reset vector fetch will commence. © 2011 Microchip Technology Inc BOR PWRT ...

Page 90

... Reset will be meaningful. Table 6-3 provides a summary of the reset flag bit operation. Set by: POR, BOR POR, BOR POR, BOR POR POR, BOR PWRSAV instruction, CLRWDT instruction, POR, BOR POR, BOR POR, BOR for more information on Cleared by: — — © 2011 Microchip Technology Inc. ...

Page 91

... The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). © 2011 Microchip Technology Inc. Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the vector table. Lower addresses generally have a higher natural priority ...

Page 92

... Table 7-1 for the list of implemented interrupt vectors. DS70291E-page 92 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 (1) (1) © 2011 Microchip Technology Inc. ...

Page 93

... Microchip Technology Inc. AIVT Address 0x000104 Reserved 0x000106 Oscillator Failure 0x000108 Address Error 0x00010A Stack Error 0x00010C Math Error 0x00010E DMA Error 0x000110 Reserved 0x000112 Reserved 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – ...

Page 94

... PWM2 – PWM2 Period Match 0x0001A8 FLTA2 – PWM2 Fault A 0x0001AA QEI2 – Position Counter Compare 0x0001AC Reserved 0x0001AE Reserved 0x0001B0 DAC1R – DAC1 Right Data Request 0x0001B2 DAC1L – DAC1 Left Data Request 0x0001B4-0x0001FE Reserved Interrupt Source © 2011 Microchip Technology Inc. ...

Page 95

... IECx The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2011 Microchip Technology Inc. 7.3.4 IPCx The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels ...

Page 96

... R/C-0 (2) ACCSAT IPL3 -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) Register 3-2. R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 R-0 R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 R/W-0 PSV RND IF bit 0 ‘1’ = Bit is set © 2011 Microchip Technology Inc. ...

Page 97

... DMA controller error trap has occurred 0 = DMA controller error trap has not occurred bit 4 MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE ...

Page 98

... STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70291E-page 98 © 2011 Microchip Technology Inc. ...

Page 99

... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 ...

Page 100

... Interrupt request has not occurred DS70291E-page 100 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF R/W-0 R/W-0 R/W-0 DMA0IF T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 101

... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011 Microchip Technology Inc. DS70291E-page 101 ...

Page 102

... Interrupt request has not occurred DS70291E-page 102 R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF R/W-0 R/W-0 R/W-0 INT1IF CNIF CMIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC3IF DMA2IF bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 103

... MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011 Microchip Technology Inc. DS70291E-page 103 ...

Page 104

... DS70291E-page 104 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (1) (1) DMA3IF C1IF C1RXIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) U-0 U-0 — — bit 8 R/W-0 R/W-0 SPI2IF SPI2EIF bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 105

... Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 PWM1IF: PWM1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 R/W-0 — — QEI1IF U-0 ...

Page 106

... DS70291E-page 106 U-0 R/W-0 R/W-0 — QEI2IF FLTA2IF R/W-0 R/W-0 R/W-0 DMA6IF CRCIF U2EIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (2) (1) R/W-0 U-0 PWM2IF — bit 8 R/W-0 U-0 U1EIF — bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 107

... DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE R/W-0 ...

Page 108

... Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Flag Status bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70291E-page 108 © 2011 Microchip Technology Inc. ...

Page 109

... INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T5IE T4IE OC4IE R/W-0 R/W-0 ...

Page 110

... Interrupt request not enabled bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70291E-page 110 © 2011 Microchip Technology Inc. ...

Page 111

... Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Note 1: Interrupts are disabled on devices without ECAN™ modules. © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...

Page 112

... Unimplemented: Read as ‘0’ DS70291E-page 112 U-0 U-0 R/W-0 — — QEI1IE U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. R/W-0 U-0 PWM1IE — bit 8 U-0 U-0 — — bit Bit is unknown ...

Page 113

... Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ Note 1: Interrupts are disabled on devices without ECAN™ modules. 2: Interrupts are disabled on devices without Audio DAC modules. © 2011 Microchip Technology Inc. U-0 R/W-0 R/W-0 — QEI2IE FLTA2IE R/W-0 ...

Page 114

... Interrupt is priority 1 000 = Interrupt source is disabled DS70291E-page 114 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 115

... Unimplemented: Read as ‘0’ bit 2-0 DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

Page 116

... Interrupt is priority 1 000 = Interrupt source is disabled DS70291E-page 116 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 117

... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — ...

Page 118

... Interrupt is priority 1 000 = Interrupt source is disabled DS70291E-page 118 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 CMIP<2:0> bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 119

... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — ...

Page 120

... Interrupt is priority 1 000 = Interrupt source is disabled DS70291E-page 120 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC4IP<2:0> bit 8 R/W-0 R/W-0 DMA2IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 121

... Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...

Page 122

... Interrupts disabled on devices without ECAN™ modules. DS70291E-page 122 R/W-0 U-0 R/W-1 (1) — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 (1) C1RXIP<2:0> bit 8 R/W-0 R/W-0 SPI2EIP<2:0> bit Bit is unknown (1) © 2011 Microchip Technology Inc. ...

Page 123

... Unimplemented: Read as ‘0’ bit 2-0 DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — ...

Page 124

... Unimplemented: Read as ‘0’ DS70291E-page 124 U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 DMA4IP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 125

... PWM1IP<2:0>: PWM1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — ...

Page 126

... Unimplemented: Read as ‘0’ DS70291E-page 126 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RTCIP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 127

... U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — ...

Page 128

... Interrupts are disabled on devices without ECAN™ modules. DS70291E-page 128 U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 (1) C1TXIP<2:0> bit 8 R/W-0 R/W-0 DMA6IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 129

... PWM2IP<2:0>: PWM2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-0 — R/W-0 U-0 U-0 — — ...

Page 130

... Interrupts are disabled on devices without Audio DAC modules. DS70291E-page 130 R/W-0 U-0 R/W-0 (1) — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) R/W-0 R/W-0 (1) DAC1RIP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 131

... Unimplemented: Read as ‘0’ bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 © 2011 Microchip Technology Inc. U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM< ...

Page 132

... Only user interrupts with a priority level lower can be disabled. Trap sources (level 8-level 15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. © 2011 Microchip Technology Inc. ...

Page 133

... PMP - Master Data Transfer ECAN1 – TX Data Request DAC1 - Right Data Output DAC2 - Left Data Output © 2011 Microchip Technology Inc. Direct Memory Access (DMA very efficient mech- anism of copying data between peripheral SFRs (e.g., UART Receive register, Input Capture 1 buffer), and buffers or variables stored in RAM, with minimal CPU intervention ...

Page 134

... Alternatively, an interrupt can be generated when half of the block has been filled. Peripheral Indirect Address DMA Controller DMA Channels DMA DS Bus DMA Ready Peripheral 3 CPU DMA CPU DMA CPU DMA DMA DMA Ready Ready Peripheral 2 Peripheral 1 © 2011 Microchip Technology Inc. ...

Page 135

... DMACS1, are common to all DMAC channels. DMACS0 contains the DMA RAM and SFR write collision flags, XWCOLx and PWCOLx, respectively. DMACS1 indicates DMA channel and Ping-Pong mode status. © 2011 Microchip Technology Inc. The DMAxCON, DMAxREQ, DMAxPAD DMAxCNT are all conventional read/write registers. ...

Page 136

... Continuous, Ping-Pong modes disabled DS70291E-page 136 R/W-0 R/W-0 HALF NULLW R/W-0 U-0 AMODE<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 R/W-0 — MODE<1:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 137

... The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced DMA transfer is complete. 2: Refer to Table 7-1 for a complete listing of IRQ numbers for all interrupt sources. © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — ...

Page 138

... Bit is cleared R/W-0 R/W-0 R/W-0 STB<15:8> R/W-0 R/W-0 R/W-0 STB<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 139

... CNT<9:0>: DMA Transfer Count Register bits Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. 2: Number of DMA transfers = CNT<9:0> © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PAD<15:8> R/W-0 R/W-0 R/W-0 PAD< ...

Page 140

... R/C-0 R/C-0 R/C-0 PWCOL4 PWCOL3 PWCOL2 R/C-0 R/C-0 R/C-0 XWCOL4 XWCOL3 XWCOL2 C = Clear only bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/C-0 R/C-0 PWCOL1 PWCOL0 bit 8 R/C-0 R/C-0 XWCOL1 XWCOL0 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 141

... Write collision detected write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected © 2011 Microchip Technology Inc. DS70291E-page 141 ...

Page 142

... DMA0STB register selected 0 = DMA0STA register selected DS70291E-page 142 U-0 R-1 R-1 — LSTCH<3:0> R-0 R-0 R-0 PPST4 PPST3 PPST2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-1 R-1 bit 8 R-0 R-0 PPST1 PPST0 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 143

... R-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits © 2011 Microchip Technology Inc. R-0 R-0 R-0 DSADR<15:8> R-0 R-0 R-0 DSADR<7:0> Unimplemented bit, read as ‘0’ ...

Page 144

... AND dsPIC33FJ128MCX02/X04 NOTES: DS70291E-page 144 © 2011 Microchip Technology Inc. ...

Page 145

... Doze mode used in any ratio other than 1:1, which is the default. © 2011 Microchip Technology Inc. • External and internal oscillator options as clock sources • An on-chip Phase-Locked Loop (PLL) to scale the internal operating frequency to the required ...

Page 146

... External Clock (EC): External clock signal Mhz. The external clock signal is directly applied to SOSCI pin. Section 28.1 “Configuration Configuration bits, FNOSC<2:0> bits, POSCMD<1:0> Table 9-1. is divided by OSC ) and defines the P CY and , is given by: DEVICE OPERATING FREQUENCY F OSC ------------- © 2011 Microchip Technology Inc. ...

Page 147

... X04 PLL BLOCK DIAGRAM Source (Crystal, External Clock or Internal RC) Note 1: This frequency range must be satisfied at all times. © 2011 Microchip Technology Inc. For a primary oscillator or FRC oscillator, output ‘F the PLL output ‘F EQUATION 9-2: For example, suppose a 10 MHz crystal is being used with the selected oscillator mode of XT with PLL. • ...

Page 148

... DS70291E-page 148 Oscillator Source POSCMD<1:0> Internal xx Internal xx Internal xx ) Secondary xx Primary 10 Primary 01 Primary 00 Primary 10 Primary 01 Primary 00 Internal xx Internal xx See FNOSC<2:0> Note 1, 2 111 1 110 1 101 1 100 — 011 — 011 1 011 — 010 — 010 1 010 1 001 1 000 © 2011 Microchip Technology Inc. ...

Page 149

... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: This register is reset only on a Power-on Reset (POR). © 2011 Microchip Technology Inc. (1,3) R-0 U-0 R/W-y — ...

Page 150

... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: This register is reset only on a Power-on Reset (POR). DS70291E-page 150 (1,3) (CONTINUED) © 2011 Microchip Technology Inc. ...

Page 151

... Input/33 • • • 00001 = Input/3 00000 = Input/2 (default) Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. 2: This register is reset only on a Power-on Reset (POR). © 2011 Microchip Technology Inc. (2) R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE< ...

Page 152

... This register is reset only on a Power-on Reset (POR). DS70291E-page 152 (1) U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 R/W-0 — PLLDIV<8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 153

... OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. 2: This register is reset only on a Power-on Reset (POR). © 2011 Microchip Technology Inc. (2) U-0 U-0 U-0 — ...

Page 154

... U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) provides the source clock for the Auxiliary Clock Divider (1) R/W-0 R/W-0 R/W-0 APSTSCLR<2:0> bit 8 U-0 U-0 U-0 — — — bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 155

... NOSC control bits. If they are the same, the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. © 2011 Microchip Technology Inc valid clock switch has been initiated, the LOCK (OSCCON<3>) status bits are cleared. ...

Page 156

... AND dsPIC33FJ128MCX02/X04 NOTES: DS70291E-page 156 © 2011 Microchip Technology Inc. ...

Page 157

... Section 9.0 “Oscillator Configuration”. EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2011 Microchip Technology Inc. 10.2 Instruction-Based Power-Saving Modes dsPIC33FJ32MC302/304, and and dsPIC33FJ128MCX02/X04 devices have two family ...

Page 158

... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control regis- ters are already configured to enable module operation). There are eight possible ® DSC © 2011 Microchip Technology Inc. ...

Page 159

... SPI2MD: SPI2 Module Disable bit 1 = SPI2 module is disabled 0 = SPI2 module is enabled bit 3 SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T2MD T1MD QEI1MD R/W-0 R/W-0 ...

Page 160

... AND dsPIC33FJ128MCX02/X04 REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED) bit 1 C1MD: ECAN1 Module Disable bit 1 = ECAN1 module is disabled 0 = ECAN1 module is enabled bit 0 AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled DS70291E-page 160 © 2011 Microchip Technology Inc. ...

Page 161

... OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 ...

Page 162

... Unimplemented: Read as ‘0’ DS70291E-page 162 U-0 U-0 R/W-0 — — CMPMD R/W-0 U-0 U-0 PWM2MD — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RTCCMD PMPMD bit 8 U-0 U-0 — — bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 163

... WR Port Data Latch Read LAT Read Port © 2011 Microchip Technology Inc. has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through”, in which a port’s digital output can drive the input of a peripheral that shares the same pin. ...

Page 164

... CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. Example 11-1. dsPIC33FJ32MC302/304, © 2011 Microchip Technology Inc. ...

Page 165

... The association of a peripheral to a peripheral select- able pin is handled in two different ways, depending on whether an input or output is being mapped. © 2011 Microchip Technology Inc. 11.6.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it is mapped to ...

Page 166

... SS2 RPINR23 CIRX RPINR26 (1) Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> T4CKR<4:0> T5CKR<4:0> IC1R<4:0> IC2R<4:0> IC7R<4:0> IC8R<4:0> OCFAR<4:0> FLTA1R<4:0> FLTA2R<4:0> QEA1R<4:0> QEB1R<4:0> INDX1R<4:0> QEA2R<4:0> QEB2R<4:0> INDX2R<4:0> U1RXR<4:0> U1CTSR<4:0> U2RXR<4:0> U2CTSR<4:0> SDI1R<4:0> SCK1R<4:0> SS1R<4:0> SDI2R<4:0> SCK2R<4:0> SS2R<4:0> CIRXR<4:0> © 2011 Microchip Technology Inc. ...

Page 167

... SS1 SDO2 SCK2 SS2 C1TX OC1 OC2 OC3 OC4 UPDN1 UPDN2 © 2011 Microchip Technology Inc. FIGURE 11-3: U1TX Output enable 11-33). The U1RTS Output enable 4 UPDN2 Output enable U1TX Output U1RTS Output 4 UPDN2 Output RPn tied to default port pin 00000 ...

Page 168

... Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows user applications unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. built-in C © 2011 Microchip Technology Inc. ...

Page 169

... INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. IOLOCK bit to ‘0’. See Register R/W-1 R/W-1 INT1R<4:0> ...

Page 170

... Input tied to RP1 00000 = Input tied to RP0 DS70291E-page 170 U-0 U-0 — — R/W-1 R/W-1 INTR2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 171

... T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 T2CKR<4:0> Unimplemented bit, read as ‘0’ ...

Page 172

... Input tied to RP1 00000 = Input tied to RP0 DS70291E-page 172 R/W-1 R/W-1 T5CKR<4:0> R/W-1 R/W-1 T4CKR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 173

... IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25. • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 IC1R<4:0> Unimplemented bit, read as ‘0’ ...

Page 174

... Input tied to RP1 00000 = Input tied to RP0 DS70291E-page 174 R/W-1 R/W-1 IC8R<4:0> R/W-1 R/W-1 IC7R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 175

... FLTA1R<4:0>: Assign PWM1 Fault (FLTA1) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 OCFAR<4:0> Unimplemented bit, read as ‘0’ ...

Page 176

... Input tied to RP1 00000 = Input tied to RP0 DS70291E-page 176 U-0 U-0 — — R/W-1 R/W-1 FLTA2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 177

... QEA1R<4:0>: Assign A(QEA1) to the corresponding pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 QEB1R<4:0> R/W-1 R/W-1 QEA1R<4:0> Unimplemented bit, read as ‘0’ ...

Page 178

... Input tied to RP1 00000 = Input tied to RP0 DS70291E-page 178 U-0 U-0 — — R/W-1 R/W-1 INDX1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 179

... QEA2R<4:0>: Assign A(QEA2) to the corresponding pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 QEB2R<4:0> R/W-1 R/W-1 QEA2R<4:0> Unimplemented bit, read as ‘0’ ...

Page 180

... Input tied to RP1 00000 = Input tied to RP0 DS70291E-page 180 U-0 U-0 — — R/W-1 R/W-1 INDX2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 181

... U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 U1RXR<4:0> Unimplemented bit, read as ‘0’ ...

Page 182

... Input tied to RP1 00000 = Input tied to RP0 DS70291E-page 182 R/W-1 R/W-1 U2CTSR<4:0> R/W-1 R/W-1 U2RXR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 183

... SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 SDI1R<4:0> Unimplemented bit, read as ‘0’ ...

Page 184

... Input tied to RP1 00000 = Input tied to RP0 DS70291E-page 184 U-0 U-0 — — R/W-1 R/W-1 SS1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 185

... SDI2R<4:0>: Assign SPI2 Data Input (SDI2) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 SCK2R<4:0> R/W-1 R/W-1 SDI2R<4:0> Unimplemented bit, read as ‘0’ ...

Page 186

... C1RXR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown (1) U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 187

... RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see peripheral function numbers) © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP1R<4:0> R/W-0 R/W-0 R/W-0 RP0R< ...

Page 188

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for © 2011 Microchip Technology Inc. ...

Page 189

... RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see peripheral function numbers) © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP9R<4:0> R/W-0 R/W-0 R/W-0 RP8R< ...

Page 190

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for © 2011 Microchip Technology Inc. ...

Page 191

... Unimplemented: Read as ‘0’ bit 4-0 RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits (see peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP17R<4:0> R/W-0 R/W-0 R/W-0 RP16R< ...

Page 192

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for © 2011 Microchip Technology Inc. ...

Page 193

... Unimplemented: Read as ‘0’ bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP25R<4:0> R/W-0 R/W-0 R/W-0 RP24R< ...

Page 194

... AND dsPIC33FJ128MCX02/X04 NOTES: DS70291E-page 194 © 2011 Microchip Technology Inc. ...

Page 195

... TCKPS<1:0> SOSCI (1) LPOSCEN Note 1: Refer to Section 9.0 “Oscillator Configuration” © 2011 Microchip Technology Inc. The unique features of Timer1 allow used for Real-Time Clock (RTC) applications. A block diagram of Timer1 is shown in The Timer1 module can operate in one of the following and modes: ...

Page 196

... Unimplemented: Read as ‘0’ DS70291E-page 196 U-0 U-0 — — R/W-0 U-0 TCKPS<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TSYNC TCS — bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 197

... F CY TCKPS<1:0> Prescaler Sync TxCK TCKPS<1:0> © 2011 Microchip Technology Inc. Timer2 and Timer4 are Type B timers with the following specific features: • A Type B timer can be concatenated with a Type C timer to form a 32-bit timer • The external clock input (TxCK) is always and ...

Page 198

... The timer value at any point is stored in the register pair, TMR3:TMR2 or TMR5:TMR4, which always contains the most significant word of the count, while TMR2 or TMR4 contains the least significant word. Table 13-2. 32-BIT TIMER TYPE C Timer (msw) Timer3 Timer5 13-3. The 32-timer module can © 2011 Microchip Technology Inc. ...

Page 199

... F CY (/n) TCKPS<1:0> Prescaler Sync (/n) TxCK TCKPS<1:0> Note 1: ADC trigger is available only on TMR3:TMR2 and TMR5:TMR2 32-bit timers. 2: Timer Type B Timer ( and 4). 3: Timer Type C Timer ( and 5). © 2011 Microchip Technology Inc. Falling Edge Detect PRy PRx Comparator 10 lsw TMRx TMRy 00 x1 TMRyHLD ...

Page 200

... Unimplemented: Read as ‘0’ DS70291E-page 200 U-0 U-0 — — R/W-0 R/W-0 TCKPS<1:0> T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2011 Microchip Technology Inc. ...

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