IC PIC MCU FLASH 32KX16 64TQFP

PIC24HJ64GP506-I/PT

Manufacturer Part NumberPIC24HJ64GP506-I/PT
DescriptionIC PIC MCU FLASH 32KX16 64TQFP
ManufacturerMicrochip Technology
SeriesPIC® 24H
PIC24HJ64GP506-I/PT datasheets
 


Specifications of PIC24HJ64GP506-I/PT

Program Memory TypeFLASHProgram Memory Size64KB (22K x 24)
Package / Case64-TFQFPCore ProcessorPIC
Core Size16-BitSpeed40 MIPs
ConnectivityCAN, I²C, IrDA, LIN, SPI, UART/USARTPeripheralsBrown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o53Ram Size8K x 8
Voltage - Supply (vcc/vdd)3 V ~ 3.6 VData ConvertersA/D 18x10b/12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesPIC24HJCorePIC
Data Bus Width16 bitData Ram Size8 KB
Interface Type3-Wire/I2C/USARTMaximum Clock Frequency40 MHz
Number Of Programmable I/os53Number Of Timers13
Operating Supply Voltage0 V to 2.5 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By SupplierPG164130, DV164035, DV244005, DV164005Minimum Operating Temperature- 40 C
On-chip Adc18-ch x 12-bitController Family/seriesPIC24
No. Of I/o's53Ram Memory Size8KB
Cpu Speed40MIPSNo. Of Timers13
Embedded Interface TypeCAN, I2C, SPI, UARTRohs CompliantYes
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
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dsPIC33F/PIC24H Flash Programming Specification
1.0
DEVICE OVERVIEW
This document defines the programming specification
for the dsPIC33F 16-bit Digital Signal Controller (DSC)
and PIC24H 16-bit Microcontroller (MCU) families. This
programming specification is required only for those
developing programming support for the dsPIC33F/
PIC24H family. Customers using only one of these
devices should use development tools that already
provide support for device programming.
Topics covered include:
1.0
Device Overview ......................................................... 1
2.0
Programming Overview of the dsPIC33F/PIC24H ...... 1
3.0
Device Programming – Enhanced ICSP ..................... 8
4.0
The Programming Executive ..................................... 19
5.0
Device Programming – ICSP .................................... 28
6.0
Programming the Programming Executive
to Memory ................................................................. 45
7.0
Device ID................................................................... 50
8.0
AC/DC Characteristics and Timing Requirements .... 54
Appendix A: Hex File Format .............................................. 57
Appendix B: Device ID Register Silicon Errata Addendum . 58
Appendix C: Diagnostic and Calibration Registers ............. 59
Appendix D: Checksum Computation ................................. 61
Appendix E: Revision History.............................................. 74
2.0
PROGRAMMING OVERVIEW
OF THE dsPIC33F/PIC24H
There are two methods of programming the dsPIC33F/
PIC24H
family
of
devices
discussed
programming specification. They are:
• In-Circuit Serial Programming™ (ICSP™)
programming capability
• Enhanced In-Circuit Serial Programming
The ICSP programming method is the most direct
method to program the device; however, it is also the
slower of the two methods. It provides native, low-level
programming capability to erase, program and verify
the chip.
The Enhanced ICSP protocol uses a faster method that
takes advantage of the programming executive, as
illustrated in
Figure
2-1. The programming executive
provides all the necessary functionality to erase,
program and verify the chip through a small command
set. The command set allows the programmer to
program
the
dsPIC33F/PIC24H
Specification devices without having to deal with the
low-level programming protocols of the chip.
© 2010 Microchip Technology Inc.
dsPIC33F/PIC24H
FIGURE 2-1:
Programmer
This specification is divided into major sections that
describe the programming methods independently.
Section 3.0 “Device Programming – Enhanced
ICSP”
describes the Enhanced ICSP method.
Section 5.0
describes the ICSP method.
2.1
Power Requirements
All devices in the dsPIC33F/PIC24H family are dual
voltage supply designs: one supply for the core and
another for the peripherals and I/O pins. A regulator is
provided on-chip to alleviate the need for two external
voltage supplies.
All of the dsPIC33F/PIC24H devices power their core
digital logic at a nominal 2.5V. To simplify system
in
this
design,
all
Programming Specification family incorporate an
on-chip regulator that allows the device to run its core
logic from V
.
DD
The regulator provides power to the core from the other
V
pins. A low-ESR capacitor (such as tantalum) must
DD
be connected to the V
to maintain the stability of the regulator. The
specifications for core voltage and capacitance are
listed in
Section 8.0 “AC/DC Characteristics and
Timing
Requirements”.
Programming
PROGRAMMING SYSTEM
OVERVIEW FOR
ENHANCED ICSP™
dsPIC33F/PIC24H
Programming
Executive
On-Chip Memory
“Device
Programming
ICSP”
devices
in
the
dsPIC33F/PIC24H
pin
(Figure
2-2). This helps
CAP
DS70152H-page 1

PIC24HJ64GP506-I/PT Summary of contents

  • Page 1

    ... The command set allows the programmer to program the dsPIC33F/PIC24H Specification devices without having to deal with the low-level programming protocols of the chip. © 2010 Microchip Technology Inc. dsPIC33F/PIC24H FIGURE 2-1: Programmer This specification is divided into major sections that describe the programming methods independently. ...

  • Page 2

    ... Primary Programming Pin Pair: Serial Data I Secondary Programming Pin Pair: Serial Clock I/O Secondary Programming Pin Pair: Serial Data I Tertiary Programming Pin Pair: Serial Clock I/O Tertiary Programming Pin Pair: Serial Data P = Power program memory word can Pin Description ) and ground DD © 2010 Microchip Technology Inc. be ...

  • Page 3

    ... Microchip Technology Inc. device programming and the debug executive is used for in-circuit debugging. This region of memory cannot be used to store user code. Locations 0xF80000 through 0xF80017 are reserved for the device Configuration registers. ...

  • Page 4

    ... Microchip Technology Inc. ...

  • Page 5

    ... PIC24HJ64GP206A 0x00ABFE (22K) PIC24HJ64GP210A 0x00ABFE (22K) PIC24HJ64GP506A 0x00ABFE (22K) PIC24HJ64GP510A 0x00ABFE (22K) dsPIC33FJ128GP206A 0x0157FE (44K) dsPIC33FJ128GP306A 0x0157FE (44K) dsPIC33FJ128GP310A 0x0157FE (44K) dsPIC33FJ128GP706A 0x0157FE (44K) dsPIC33FJ128GP708A 0x0157FE (44K) ...

  • Page 6

    ... Microchip Technology Inc. ...

  • Page 7

    ... FIGURE 2-3: PROGRAM MEMORY MAP Note: The address boundaries for user Flash and Executive code memory are device dependent. © 2010 Microchip Technology Inc. 0x000000 User Flash Code Memory (87552 x 24-bit) 0x02ABFE 0x02AC00 Reserved 0x7FFFFE 0x800000 Executive Code Memory (2048 x 24-bit) ...

  • Page 8

    ... Program Configuration Bits Specification can HIGH-LEVEL ENHANCED ICSP™ PROGRAMMING FLOW Start Perform Bulk Erase (using ICSP™) Program PE Into Executive Memory (using ICSP) Enter Enhanced ICSP Program Memory Verify Program Verify Configuration Bits Exit Enhanced ICSP End © 2010 Microchip Technology Inc. be ...

  • Page 9

    ... Sanity Check End Note 1: See TABLE 7-1: “Device IDs and Revi- sion” for the Application ID of each device. © 2010 Microchip Technology Inc. 3.3 Entering Enhanced ICSP Mode As illustrated in Figure Program/Verify mode requires three steps: 1. The MCLR pin is briefly driven high then low. ...

  • Page 10

    ... P19 commands to send (called After the first command successfully, ‘RemainingCmds’ bootloader code must not be itself. Instead, program the © 2010 Microchip Technology Inc ...

  • Page 11

    ... Is No RemainingCmds ‘0’? Yes End © 2010 Microchip Technology Inc. 3.5.2 PROGRAMMING VERIFICATION After code memory is programmed, the contents of memory can be verified to ensure that programming was successful. Verification requires code memory to be read back and compared against the copy held in the programmer’ ...

  • Page 12

    ... The register descriptions for the FBS, FSS, FGS, FOSCSEL, FOSC, FWDT, FPOR Configuration registers are shown in Note 1: If any of the code-protect bits in FBS, FSS or FGS is clear, the entire device must be erased before it can be reprogrammed. Description © 2010 Microchip Technology Inc. and FICD Table 3-2. ...

  • Page 13

    ... FGS General Segment Write-Protect bit 1 = General Segment program memory is not write-protected 0 = General Segment program memory is write-protected © 2010 Microchip Technology Inc. Description N) bytes of RAM are reserved for Secure Segment in all other devices.] – N) bytes of RAM are reserved for Secure Segment in all other devices.] – ...

  • Page 14

    ... PWMPIN FPOR Motor Control PWM Module Pin mode 1 = PWM module pins controlled by PORT register at device Reset (tri-stated PWM module pins controlled by PWM module at device Reset (configured as output pins) DS70152H-page 14 Description © 2010 Microchip Technology Inc. ...

  • Page 15

    ... Hysteresis is applied to falling edge 0 = Hysteresis is applied to rising edge HYST1<1:0> FCMP Comparator Hysteresis Select Hysteresis Hysteresis Hysteresis Hysteresis — All Unimplemented (read as ‘0’, write as ‘0’) © 2010 Microchip Technology Inc. Description 2 C™ pins 2 C mapped to SDA1/SCL1 pins 2 C mapped to ASDA1/SACL1 pins DS70152H-page 15 ...

  • Page 16

    ... GSS<1:0> GWRP — FNOSC<2:0> — OSCIOFNC POSCMD<1:0> WDTPOST<3:0> (2) FPWRT<2:0> — — ICS<1:0> ® ICD 2 and REAL Bit 3 Bit 2 Bit 1 Bit 0 BSS<2:0> BWRP (1) — GSS<1:0> GWRP — FNOSC<2:0> — OSCIOFNC POSCMD<1:0> WDTPOST<3:0> — FPWRT<2:0> — — ICS<1:0> © 2010 Microchip Technology Inc. ...

  • Page 17

    ... These bits are reserved and always read as ‘1’. 3: The JTAGEN bit is set to ‘1’ by factory default. Microchip programmers such as MPLAB ICD 2 and REAL ICE in-circuit emulator clear this bit by default when connecting to a device. © 2010 Microchip Technology Inc. Bit 6 Bit 5 Bit 4 — ...

  • Page 18

    ... GSS<1:0> GWRP FNOSC<2:0> — OSCIOFNC POSCMD<1:0> WDTPOST<3:0> — FPWRT<2:0> — — ICS<1:0> Bit 3 Bit 2 Bit 1 Bit 0 BSS<2:0> BWRP SSS<2:0> SWRP — GSS<1:0> GWRP FNOSC<2:0> — OSCIOFNC POSCMD<1:0> WDTPOST<3:0> — FPWRT<2:0> — — ICS<1:0> © 2010 Microchip Technology Inc. ...

  • Page 19

    ... The JTAGEN bit is set to ‘1’ by factory default. Microchip programmers such as MPLAB ICD 2 and REAL ICE in-circuit emulator clear this bit by default when connecting to a device. 3: These bits are reserved on dsPIC33FJXXXGS406 devices and always read as ‘1’. © 2010 Microchip Technology Inc. Bit 6 Bit 5 Bit 4 — ...

  • Page 20

    ... GSS0 GWRP — FNOSC<2:0> — OSCIOFNC POSCMD<1:0> WDTPOST<3:0> — FPWRT<2:0> — — ICS<1:0> Bit 3 Bit 2 Bit 1 Bit 0 BSS<2:0> BWRP SSS<2:0> SWRP — GSS1 GSS0 GWRP — FNOSC<2:0> — OSCIOFNC POSCMD<1:0> WDTPOST<3:0> — FPWRT<2:0> — — ICS<1:0> © 2010 Microchip Technology Inc. ...

  • Page 21

    ... CONFIGURATION BIT PROGRAMMING FLOW ConfigAddress = ConfigAddress + 2 Note 1: For dsPIC33FJ06GS101/102/202, dsPIC33FJ16GS402/404/502/504, dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices, the Configuration address is 0xF80014. © 2010 Microchip Technology Inc. 3.6.3 PROGRAMMING VERIFICATION After the Configuration bits are programmed, the contents of memory should be verified to ensure that the programming was successful. Verification requires the Configuration bits to be read back and compared against the copy held in the programmer’ ...

  • Page 22

    ... P16 should elapse between the last clock and program signals on PGCx and PGDx before removing V FIGURE 3-6: MCLR V DD PGDx PGCx sections are IH Figure 3-6. The only . IH EXITING ENHANCED ICSP™ MODE P16 P17 PGDx = Input © 2010 Microchip Technology Inc. ...

  • Page 23

    ... MSb © 2010 Microchip Technology Inc. Since a 2-wire SPI is used, and data transmissions are bidirectional, a simple protocol is used to control the direction of PGDx. When the programmer completes a command transmission, it releases the PGDx line and allows the programming executive to drive this line high ...

  • Page 24

    ... Figure 4-4. This PACKED INSTRUCTION WORD FORMAT 8 7 LSW1 MSB1 LSW2 When the number of instruction words transferred is odd, MSB2 is zero and LSW2 cannot be transmitted. PROGRAMMING EXECUTIVE ERROR HANDLING executive will “NACK” Section 4.3.1.3 “QE_Code © 2010 Microchip Technology Inc. 0 all ...

  • Page 25

    ... Note: This instruction is not required for programming, but is development purposes only. © 2010 Microchip Technology Inc. Time Out 1 ms Sanity check Read an 8-bit word from the specified Configuration register or Device ID register. 1 ms/row Read ‘N’ 24-bit instruction words of code memory starting from the specified address ...

  • Page 26

    ... MSB of program memory word N (zero padded) Note: Reading unimplemented memory will cause the programming executive to reset. Please ensure that only memory locations present on a particular device are accessed. © 2010 Microchip Technology Inc Length N Addr_MSB Description Format”. 1)/2 words ...

  • Page 27

    ... After the specified data word has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. Expected Response (2 words): 0x1400 0x0002 © 2010 Microchip Technology Inc. 4.2.9 PROGP COMMAND Opcode ...

  • Page 28

    ... Data is shifted in a packed method as demonstrated in Figure Significant Byte first. Example: CRC-CITT-16 with test data of “123456789” becomes 0x29B1 Expected Response (3 words): QE_Code: 0x1C00 Length: 0x0003 CRC Value: 0xXXXX © 2010 Microchip Technology Inc Length Addr_MSB Size_MSB Description 4-4, byte-wise Least ...

  • Page 29

    ... Expected Response (2 words for non-blank device): 0x1E0F 0x0002 Note: The QBLANK command does not check the system operation Configuration bits since these bits are not set to ‘1’ when a Chip Erase is performed. © 2010 Microchip Technology Inc. 4.2.13 QVER COMMAND Opcode Field ...

  • Page 30

    ... If the verify of the programming for the PROGP or PROGC command fails, the QE_Code is set to 0x1. For all other programming executive errors, the QE_Code is 0x2. © 2010 Microchip Technology Inc. processed. Since the can only ...

  • Page 31

    ... Data Format”. When reading an odd num- ber of program memory words (N odd), the response to the READP command 1)/ words. When reading an even number of program memory words (N even), the response to the READP command N words. © 2010 Microchip Technology Inc. Section 4.2.2 DS70152H-page 31 ...

  • Page 32

    ... Then, program the code-protect Configuration bits, if required. for more FIGURE 5-1: Program Configuration Bits HIGH-LEVEL ICSP™ PROGRAMMING FLOW Start Enter ICSP™ Perform Bulk Erase Program Memory Verify Program Verify Configuration Bits Exit ICSP End © 2010 Microchip Technology Inc. ...

  • Page 33

    ... REGOUT Shift out the VISI register. 0010b-1111b N/A Reserved. © 2010 Microchip Technology Inc. 5.3.1 The SIX control code allows execution of dsPIC33F/ PIC24H Programming Specification assembly instruc- (1) . tions. When the SIX code is received, the CPU is sus- pended for 24 clock cycles, as the instruction is then clocked into the internal buffer ...

  • Page 34

    ... Shift Out VISI Register<15:0> PGDx = Output P4a MSB Execute 24-bit Instruction, Fetch Next Control Code P4a MSB Execute 24-bit Instruction, Fetch Next Control Code P4a MSb Execution Takes Place, Fetch Next Control Code PGDx = Input © 2010 Microchip Technology Inc ...

  • Page 35

    ... FIGURE 5-5: ENTERING ICSP™ MODE P6 P21 P14 MCLR V DD PGDx PGCx P18 © 2010 Microchip Technology Inc. TABLE 5-3: NVMCON Value 0x4001 0x4000 write operation 0x4003 5.4.2 The WR bit (NVMCON<15>) is used to start an erase or write cycle. Setting the WR bit initiates the programming cycle ...

  • Page 36

    ... All other combinations of NVMOP<3:0> are unimplemented. DS70152H-page 36 (1) U-0 U-0 — — (1) U-0 R/W-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) U-0 U-0 U-0 — — — bit 8 (1) (1) (1) R/W-0 R/W-0 R/W-0 (2) NVMOP<3:0> bit Bit is unknown © 2010 Microchip Technology Inc. ...

  • Page 37

    ... For example, the user may want to erase the code in the General Segment without erasing a bootloader located in the Boot Segment. © 2010 Microchip Technology Inc. The Secure Segment Erase command is used to erase the Secure Segment and the FSS Configuration register. The General Segment Erase command is used to erase the General Segment and the FGS Configuration register ...

  • Page 38

    ... Lastly, in Step 10, Steps 3-9 are repeated until all of code memory is programmed. FIGURE 5-7: Figure 5-2 MSB1 MSB3 W5 PACKED INSTRUCTION WORDS IN W0: LSW0 MSB0 LSW1 LSW2 MSB2 LSW3 © 2010 Microchip Technology Inc. ...

  • Page 39

    ... Step 7: Initiate the write cycle. 0000 A8E761 BSET 0000 000000 NOP 0000 000000 NOP 0000 000000 NOP 0000 000000 NOP © 2010 Microchip Technology Inc. Description 0x200 0x200 #0x4001, W10 W10, NVMCON #<DestinationAddress23:16>, W0 W0, TBLPAG #<DestinationAddress15:0>, W7 #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 #<LSW2>, W3 #<MSB3:MSB2>, W4 #<LSW3>, W5 NVMCON, #WR ...

  • Page 40

    ... Requirements”) to allow sufficient time for the Row Program operation to NVMCON, W0 W0, VISI 0x200 Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> All No bytes written? Yes Start Write Sequence and Poll for WR bit to be cleared All No locations done? Yes End © 2010 Microchip Technology Inc. ...

  • Page 41

    ... Microchip Technology Inc. The FBS, FSS and FGS Configuration registers are special since they enable code protection for the device. For security purposes, once any bit in these registers is programmed to ‘0’ (to enable code protection), it can only be set back to ‘1’ by performing ...

  • Page 42

    ... FOSC FWDT FPOR FICD FCMP Name FBS FSS FGS FOSCSEL FOSC FWDT FPOR FICD FUID0 FUID1 FUID2 FUID3 © 2010 Microchip Technology Inc. Default Value 0x0F (1) 0xCF/0xFF 0x07 0x87 0xE7 0xDF 0xF7 0xE3 0xFF 0xFF 0xFF 0xFF Default Value 0x0F 0x07 ...

  • Page 43

    ... TBLWTL instruction. In Steps 7 and 8, the programming cycle is initiated. In Step 9, the internal PC is set to 0x200 as a safety measure to prevent the PC from incrementing into unimplemented memory. Lastly, Steps 4-9 are repeated until all twelve Configuration registers are written. © 2010 Microchip Technology Inc. DS70152H-page 43 ...

  • Page 44

    ... Step 9: Repeat steps 5-8 until all twelve Configuration registers are written. DS70152H-page 44 Description 0x200 0x200 #0x0000, W7 #0x4000, W10 W10, NVMCON #0xF8, W0 W0, TBLPAG #<CONFIG_VALUE>, W0 NVMCON, #WR Section 8.0 “AC/DC Characteristics and Requirements”) to allow sufficient time for the Configuration Register NVMCON, W0 W0, VISI 0x200 © 2010 Microchip Technology Inc. ...

  • Page 45

    ... NOP 0000 000000 NOP © 2010 Microchip Technology Inc. To minimize the reading time, the packed instruction word format that was utilized for writing is also used for reading (see Figure W7, is initialized. In Step 4, two instruction words are read from code memory and clocked out of the device, through the VISI register, using the REGOUT command ...

  • Page 46

    ... MOV W5, VISI 0000 000000 NOP Clock out contents of VISI register. 0001 <VISI> 0000 000000 NOP Step 5: Repeat step 4 until all desired code memory is read. Step 6: Reset device internal PC. 0000 040200 GOTO 0000 000000 NOP DS70152H-page 46 Description 0x200 © 2010 Microchip Technology Inc. ...

  • Page 47

    ... GOTO 0000 000000 NOP © 2010 Microchip Technology Inc. Table 5-9 shows the ICSP programming details for reading all of the configuration memory. Note that the TBLPAG register is hard coded to 0xF8 (the upper byte address of configuration memory) and the read pointer, W6, is initialized to 0x0000 ...

  • Page 48

    ... PGCx and PGDx before removing V FIGURE 5-10: MCLR V DD PGDx PGCx Failure Report Error Table 5-10. Section 3.0 “Device ICSP”. However, if the Section 6.0 “Programming Memory”. IH Figure 5-10. The only . IH EXITING ICSP™ MODE P16 P17 PGDx = Input © 2010 Microchip Technology Inc. ...

  • Page 49

    ... BA0890 TBLRDL [W0], [W1] 0000 000000 NOP 0000 000000 NOP Step 3: Output the VISI register using the REGOUT command. Clock out contents of the VISI register. 0001 <VISI> © 2010 Microchip Technology Inc. Description 0x200 0x200 #0x80, W0 W0, TBLPAG #0x7FO, W0 #VISI, W1 DS70152H-page 49 ...

  • Page 50

    ... NVMCON, #15 Section 8.0 “AC/DC Characteristics and Requirements”) to allow sufficient time for the Page Erase operation to NVMCON, W0 W0, VISI #0x4001, W10 W10, NVMCON #0x80, W0 W0, TBLPAG W7 Table 6-1. programming executive must be erased before it is Table 6-1. © 2010 Microchip Technology Inc. ...

  • Page 51

    ... Step 9: Repeat Steps 7-8 sixteen times to load the write latches for the 64 instructions. Step 10: Initiate the programming cycle. 0000 A8E761 BSET 0000 000000 NOP 0000 000000 NOP 0000 000000 NOP 0000 000000 NOP © 2010 Microchip Technology Inc. Description #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 #<LSW2>, W3 #<MSB3:MSB2>, W4 #<LSW3> NVMCON, #15 DS70152H-page 51 ...

  • Page 52

    ... Repeat until the WR bit is clear. Step 12: Repeat Steps 7-11 until all 32 rows of executive memory are programmed. DS70152H-page 52 Description Section 8.0 “AC/DC Characteristics and Requirements”) to allow sufficient time for the Row Program operation to NVMCON, W0 W0, VISI 0x200 © 2010 Microchip Technology Inc. ...

  • Page 53

    ... TBLRDL 0000 000000 NOP 0000 000000 NOP © 2010 Microchip Technology Inc. Reading the contents of executive memory can be performed using the same technique described in has been Section 5.8 “Reading Code for reading executive memory is shown in Note that in Step 2, the TBLPAG register is set to 0x80, such that executive memory may be read ...

  • Page 54

    ... Clock out contents of VISI register. 0001 <VISI> 0000 000000 NOP Step 5: Reset the device internal PC. 0000 040200 GOTO 0000 000000 NOP Step 6: Repeat Steps 4-5 until all 2048 instruction words of executive memory are read. DS70152H-page 54 Description 0x200 © 2010 Microchip Technology Inc. ...

  • Page 55

    ... PIC24HJ64GP206 0x0041 PIC24HJ64GP210 0x0047 PIC24HJ64GP506 0x0049 PIC24HJ64GP510 0x004B © 2010 Microchip Technology Inc. Table 7-1 lists the identification information for each device. Table 7-2 shows the Device ID registers. manufacturing Register 7-1, Register 7-2 JTAG ID Type registers ...

  • Page 56

    ... Microchip Technology Inc. JTAG ID Register 7-2 Register 7-2 Register 7-3 Register 7-2 Register 7-2 Register 7-3 Register 7-1 Register 7-1 Register 7-1 Register 7-1 ...

  • Page 57

    ... PIC24HJ64GP206A 0x0041 PIC24HJ64GP210A 0x0047 PIC24HJ64GP506A 0x0049 PIC24HJ64GP510A 0x004B dsPIC33FJ128GP206A 0x00D9 dsPIC33FJ128GP306A 0x00E5 dsPIC33FJ128GP310A 0x00E7 dsPIC33FJ128GP706A 0x00ED dsPIC33FJ128GP708A 0x00EE dsPIC33FJ128GP710A 0x00EF dsPIC33FJ128MC506A 0x00A1 dsPIC33FJ128MC510A 0x00A3 dsPIC33FJ128MC706A ...

  • Page 58

    ... A0 Revision 0xCB 0xCB 0xCB 0xCB 0xCB 0xCB 0xCB Bit DEVID Value DEVREV Value 12 11 DEVID<15:0> 16 bits DEVREV<5:0> 6 bits 0x8 6 bits JTAG ID Revision Register 7-1 Register 7-1 Register 7 Manufacturer ID (0x053) 12 bits Manufacturer ID (0x053) 12 bits Manufacturer ID (0x053) 12 bits © 2010 Microchip Technology Inc ...

  • Page 59

    ... AV DD ±0. and V , respectively Time depends on the FRC accuracy and the value of the FRC Oscillator tuning register. Refer to “Electrical Characteristics” section in the specific device data sheet. © 2010 Microchip Technology Inc. Min Max 3.0 3.60 — 5 — ...

  • Page 60

    ... AV and Conditions — — See Note 2 See Note 2 See Note 2 — — — — — — — — should always be within SS © 2010 Microchip Technology Inc. ...

  • Page 61

    ... CC – two-digit hexadecimal checksum that is the two’s complement of the sum of all the preceding bytes in the line record. © 2010 Microchip Technology Inc. Because the Intel hex file format is byte-oriented, and the 16-bit program counter is not, program memory sections require special treatment. Each 24-bit pro- gram word is extended to 32 bits by inserting a so-called “ ...

  • Page 62

    ... Microchip. Steps 1 through 5 in the work around are ® implemented in MPLAB IDE version 7.61 for the MPLAB ICD 2, MPLAB REAL ICE™ in-circuit emulator and MPLAB PM3 tools. © 2010 Microchip Technology Inc. some Programming” by setting ...

  • Page 63

    ... BA1B37 0000 000000 0000 000000 Step 6: Repeat step 5 three times to read all 6 instruction words. © 2010 Microchip Technology Inc. Table C-1 provides an example of how the diagnostic and calibration registers are read. This table can be added to the programming executive between steps 1 and 2. ...

  • Page 64

    ... Externally time ‘P13’ msec (see Section 8.0 “AC/DC Characteristics and Timing Requirements”) to allow sufficient time for the Row Program operation to complete. MOV NVMCON, W0 MOV W0, VISI NOP Clock out contents of VISI register GOTO 0x200 NOP Repeat until the WR bit is clear © 2010 Microchip Technology Inc. ...

  • Page 65

    ... CFGB = Configuration Block (masked) = Byte sum of ((FBS & 0x0F) + (FGS & 0x07) + (FOSCSEL & 0x87) + (FOSC & 0xC7) + (FWDT & 0xDF) + (FPOR & 0x67) + (FICD & 0xE3)) (for dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices) © 2010 Microchip Technology Inc. Checksum Computation CFGB + SUM(0:000FFF) ...

  • Page 66

    ... Microchip Technology Inc. ...

  • Page 67

    ... CFGB = Configuration Block (masked) = Byte sum of ((FBS & 0x0F) + (FGS & 0x07) + (FOSCSEL & 0x87) + (FOSC & 0xC7) + (FWDT & 0xDF) + (FPOR & 0x67) + (FICD & 0xE3)) (for dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices) © 2010 Microchip Technology Inc. Checksum Computation CFGB + SUM(0:00ABFF) ...

  • Page 68

    ... Microchip Technology Inc. ...

  • Page 69

    ... CFGB = Configuration Block (masked) = Byte sum of ((FBS & 0x0F) + (FGS & 0x07) + (FOSCSEL & 0x87) + (FOSC & 0xC7) + (FWDT & 0xDF) + (FPOR & 0x67) + (FICD & 0xE3)) (for dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices) © 2010 Microchip Technology Inc. Checksum Computation CFGB + SUM(0:0057FF) ...

  • Page 70

    ... Microchip Technology Inc. ...

  • Page 71

    ... CFGB = Configuration Block (masked) = Byte sum of ((FBS & 0x0F) + (FGS & 0x07) + (FOSCSEL & 0x87) + (FOSC & 0xC7) + (FWDT & 0xDF) + (FPOR & 0x67) + (FICD & 0xE3)) (for dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices) © 2010 Microchip Technology Inc. Checksum Computation CFGB + SUM(0:001FFF) ...

  • Page 72

    ... TABLE D-1: CHECKSUM COMPUTATION (CONTINUED) Read Code Device Protection PIC24HJ64GP504 Disabled Enabled PIC24HJ64GP506 Disabled Enabled PIC24HJ64GP510 Disabled Enabled PIC24HJ128GP202 Disabled Enabled PIC24HJ128GP204 Disabled Enabled PIC24HJ128GP206 Disabled Enabled PIC24HJ128GP210 Disabled Enabled PIC24HJ128GP306 Disabled Enabled PIC24HJ128GP310 Disabled Enabled PIC24HJ128GP502 Disabled Enabled Item Description: SUM(a:b) = Byte sum of locations inclusive (all 3 bytes of code memory) CFGB = Configuration Block (masked) = Byte sum of ((FBS & ...

  • Page 73

    ... CFGB = Configuration Block (masked) = Byte sum of ((FBS & 0x0F) + (FGS & 0x07) + (FOSCSEL & 0x87) + (FOSC & 0xC7) + (FWDT & 0xDF) + (FPOR & 0x67) + (FICD & 0xE3)) (for dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices) © 2010 Microchip Technology Inc. Checksum Computation CFGB + SUM(0:0157FF) ...

  • Page 74

    ... Disabled Enabled dsPIC33FJ64MC710A Disabled Enabled PIC24HJ64GP206A Disabled Enabled PIC24HJ64GP210A Disabled Enabled PIC24HJ64GP506A Disabled Enabled PIC24HJ64GP510A Disabled Enabled dsPIC33FJ128GP206A Disabled Enabled Item Description: SUM(a:b) = Byte sum of locations inclusive (all 3 bytes of code memory) CFGB = Configuration Block (masked) = Byte sum of ((FBS & 0x0F) + (FGS & 0x07) + (FOSCSEL & 0x87) + (FOSC & ...

  • Page 75

    ... CFGB = Configuration Block (masked) = Byte sum of ((FBS & 0x0F) + (FGS & 0x07) + (FOSCSEL & 0x87) + (FOSC & 0xC7) + (FWDT & 0xDF) + (FPOR & 0x67) + (FICD & 0xE3)) (for dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices) © 2010 Microchip Technology Inc. Checksum Computation CFGB + SUM(0:0157FF) ...

  • Page 76

    ... Microchip Technology Inc. ...

  • Page 77

    ... CFGB = Configuration Block (masked) = Byte sum of ((FBS & 0x0F) + (FGS & 0x07) + (FOSCSEL & 0x87) + (FOSC & 0xC7) + (FWDT & 0xDF) + (FPOR & 0x67) + (FICD & 0xE3)) (for dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices) © 2010 Microchip Technology Inc. Checksum Computation CFGB +SUM(0:02ABFF) ...

  • Page 78

    ... CFGB1 = Byte sum of ((FBS & 0xCD) + (FSS & 0xCF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xC7) + (FWDT & 0xFF) + (FPOR & 0xE7) + (FICD & 0xE3)) DS70152H-page 78 Checksum Computation (1) CFGB1 + SUM(0:2ABFF) – SUM(0200:07FE) Erased Value 0xFD01 © 2010 Microchip Technology Inc. ...

  • Page 79

    ... Added the P20 timing characteristic • Updated timing characteristics and references to the timing characteristics • Updated the ICSP code examples © 2010 Microchip Technology Inc. Revision E (June 2007) • Removed list of devices from first page. This document covers all released dsPIC33F/PIC24H ...

  • Page 80

    ... PIC24HJ128GP210A - dsPIC33FJ64GP708A - PIC24HJ128GP306A - dsPIC33FJ64GP710A - PIC24HJ128GP310A - dsPIC33FJ64MC506A - PIC24HJ128GP506A - dsPIC33FJ64MC508A - PIC24HJ128GP510A - dsPIC33FJ64MC510A - dsPIC33FJ256GP506A - dsPIC33FJ64MC706A - dsPIC33FJ256GP510A - dsPIC33FJ64MC710A - dsPIC33FJ256GP710A - PIC24HJ64GP206A - dsPIC33FJ256MC510A - PIC24HJ64GP210A - dsPIC33FJ256MC710A - PIC24HJ64GP506A - PIC24HJ256GP206A - PIC24HJ64GP510A - PIC24HJ256GP210A - dsPIC33FJ128GP206A - PIC24HJ256GP610A - dsPIC33FJ128GP306A - dsPIC33FJ32GS406 - dsPIC33FJ128GP310A - dsPIC33FJ32GS606 - dsPIC33FJ128GP706A - dsPIC33FJ32GS608 - dsPIC33FJ128GP708A - dsPIC33FJ32GS610 - dsPIC33FJ128GP710A - dsPIC33FJ64GS406 - dsPIC33FJ128MC506A - dsPIC33FJ64GS606 - dsPIC33FJ128MC510A - dsPIC33FJ64GS608 - dsPIC33FJ128MC706A - dsPIC33FJ64GS610 • ...

  • Page 81

    ... Table 3-3 • Added PLLKEN to FWDT in Table 3-2 Table 3-3 • Added ALTQIO and ALTSS1 to FPOR in Table 3-2 and Table 3-3 © 2010 Microchip Technology Inc. • Removed Notes for the following Configuration Bit Descriptions in - RBS - RSS (removed Note 1) Table 3-1): ...

  • Page 82

    ... Table 7-1) • Updated parameters D111, P1, P1A and P1B in the AC/DC Characteristics and Timing Requirements (see Table 8-1) • Added Checksum Computation Example When Using CodeGuard™ Security (see Table DS70152H-page 82 3-1) 5-6) Table 5-7 D-2). © 2010 Microchip Technology Inc. ...

  • Page 83

    ... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

  • Page 84

    ... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2010 Microchip Technology Inc. 08/04/10 ...