DSPIC33FJ128GP206A-I/MR Microchip Technology, DSPIC33FJ128GP206A-I/MR Datasheet - Page 233

• Manufacturer Part Number: DSPIC33FJ128GP206A-I/MR
• Description: IC DSPIC MCU/DSP 128K 64-QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP206A-I/MR

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Product: DSCs
• Processor Series: DSPIC33F
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 20-5:
REGISTER 20-6:
 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
RSE15
TSE15
R/W-0
R/W-0
R/W-0
R/W-0
RSE7
TSE7
RSE<15:0>: Receive Slot Enable bits
1 = CSDI data is received during the individual time slot n
0 = CSDI data is ignored during the individual time slot n
TSE<15:0>: Transmit Slot Enable Control bits
1 = Transmit buffer contents are sent during the individual time slot n
0 = CSDO pin is tri-stated or driven to logic ‘0’, during the individual time slot, depending on the state
RSE14
TSE14
R/W-0
R/W-0
R/W-0
R/W-0
RSE6
TSE6
of the CSDOM bit
RSCON: DCI RECEIVE SLOT CONTROL REGISTER
TSCON: DCI TRANSMIT SLOT CONTROL REGISTER
dsPIC33FJXXXGPX06A/X08A/X10A
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
RSE13
TSE13
R/W-0
R/W-0
R/W-0
R/W-0
RSE5
TSE5
RSE12
TSE12
R/W-0
R/W-0
R/W-0
R/W-0
RSE4
TSE4
Preliminary
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
RSE11
TSE11
R/W-0
R/W-0
R/W-0
R/W-0
RSE3
TSE3
RSE10
TSE10
R/W-0
R/W-0
R/W-0
R/W-0
RSE2
TSE2
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
RSE9
RSE1
TSE9
TSE1
DS70593B-page 233
R/W-0
R/W-0
R/W-0
R/W-0
RSE8
RSE0
TSE8
TSE0
bit 8
bit 0
bit 8
bit 0