PIC24HJ64GP502-E/MM Microchip Technology, PIC24HJ64GP502-E/MM Datasheet

IC PIC MCU FLASH 64K 28-QFN

PIC24HJ64GP502-E/MM

Manufacturer Part Number
PIC24HJ64GP502-E/MM
Description
IC PIC MCU FLASH 64K 28-QFN
Manufacturer
Microchip Technology
Series
PIC® 24Hr

Specifications of PIC24HJ64GP502-E/MM

Program Memory Type
FLASH
Program Memory Size
64KB (22K x 24)
Package / Case
28-QFN
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM300027
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit or 10-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164336 - MODULE SOCKET FOR PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
PIC24HJ32GP302/304,
PIC24HJ64GPX02/X04 and
PIC24HJ128GPX02/X04
Data Sheet
High-Performance,
16-bit Microcontrollers
© 2011 Microchip Technology Inc.
DS70293E

Related parts for PIC24HJ64GP502-E/MM

PIC24HJ64GP502-E/MM Summary of contents

Page 1

... PIC24HJ64GPX02/X04 and © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ128GPX02/X04 High-Performance, 16-bit Microcontrollers Data Sheet DS70293E ...

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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

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... Most peripherals support DMA On-Chip Flash and SRAM: • Flash program memory (up to 128 Kbytes) • Data SRAM ( Kbytes) • Boot, Secure and General Security for program Flash © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 Timers/Capture/Compare/PWM: • Timer/Counters five 16-bit timers: ...

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... Fully static design • 3.3V (±10%) operating voltage • Industrial and Extended temperature • Low power consumption Packaging: • 28-pin SDIP/SOIC/QFN-S • 44-pin TQFP/QFN Note: See the device variant tables for exact peripheral features per device. © 2011 Microchip Technology Inc. ...

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... The following pages show their pinout diagrams. TABLE 1: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 CONTROLLER FAMILIES Device PIC24HJ128GP504 44 128 8 PIC24HJ128GP502 28 128 8 PIC24HJ128GP204 44 128 8 PIC24HJ128GP202 28 128 8 PIC24HJ64GP504 PIC24HJ64GP502 PIC24HJ64GP204 PIC24HJ64GP202 PIC24HJ32GP304 PIC24HJ32GP302 Note 1: RAM size is inclusive of 2 Kbytes of DMA RAM for all devices except PIC24HJ32GP302/304, which include 1 Kbyte of DMA RAM ...

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... TDO/SDA1/RP9 11 18 TCK/SCL1/RP8 12 17 (1) V INT0/RP7 PGEC3/ASCL1/RP6 14 15 AN11/RP13 1 21 AN12/RP12 2 PIC24HJ32GP302 20 PGEC2/TMS/RP11 PIC24HJ64GP202 3 19 PIC24HJ64GP502 PGED2/TDI/RP10 4 18 PIC24HJ128GP202 ( CAP PIC24HJ128GP502 TDO/SDA1/RP9 Table 1 in this section for the list of available peripherals. )” for proper connection to this pin. CAP Pins are tolerant ...

Page 7

... The RPx pins can be used by any remappable peripheral. See 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (V © 2011 Microchip Technology Inc. AN11/RP13 11 23 AN12/RP12 24 10 ...

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... PIC24HJ128GP504 4 RP24 /CN20/PMA5/RC8 30 (1) 3 RP23 /CN17/PMA0/RC7 31 (1) RP22 /CN18/PMA1/RC6 SDA1/RP9 Table 1 in this section for the list of available peripherals. )” for proper connection to this pin. CAP Pins are tolerant (1) /CN13/PMRD/RB13 (1) /CN14/PMD0/RB12 (1) /CN15/PMD1/RB11 (1) /CN16/PMD2/RB10 (1) /CN21/PMD3/RB9 © 2011 Microchip Technology Inc. ...

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... High Temperature Electrical Characteristics ............................................................................................................................ 331 30.0 Packaging Information.............................................................................................................................................................. 341 Appendix A: Revision History............................................................................................................................................................. 351 Index ................................................................................................................................................................................................. 361 The Microchip Web Site ..................................................................................................................................................................... 365 Customer Change Notification Service .............................................................................................................................................. 365 Customer Support .............................................................................................................................................................................. 365 Reader Response .............................................................................................................................................................................. 366 Product Identification System ............................................................................................................................................................ 367 © 2011 Microchip Technology Inc. DS70293E-page 9 ...

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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com DS70293E-page 10 to receive the most current information on all of our products. © 2011 Microchip Technology Inc. ...

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... PIC24HJ128GPX02/X04 devices. Figure 1-1 shows a general block diagram of the core and peripheral modules PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 families of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2011 Microchip Technology Inc. and families the DS70293E-page 11 ...

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... Instruction Reg Multiplier Register Array Divide Support MCLR OC/ Timers UART1, 2 ADC1 PWM1-4 1-5 IC1 CNx I2C1 PORTA DMA RAM PORTB 16 DMA PORTC Controller Remappable Pins 16-bit ALU 16 “Pin Diagrams” for the specific pins and features © 2011 Microchip Technology Inc. ...

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... SS2 I/O ST Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select © 2011 Microchip Technology Inc. PPS Description Analog input channels. No External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...

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... Positive supply for peripheral logic and I/O pins. No CPU logic filter capacitor connection. No Ground reference for logic and I/O pins. No Analog voltage reference (high) input. No Analog voltage reference (low) input. Analog = Analog input O = Output TTL = TTL input buffer P = Power I = Input © 2011 Microchip Technology Inc. ...

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... ADC module is implemented Note: The AV and connected independent of the ADC voltage reference source. © 2011 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling ...

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... Ensure that the MCLR pin V and V specifications are met MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V and V specifications are met © 2011 Microchip Technology Inc. is ...

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... REAL ICE™ In-Circuit Emulator User’s Guide” DS51616 ® • “Using MPLAB REAL ICE™” (poster) DS51749 © 2011 Microchip Technology Inc. 2.6 External Oscillator Pins Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Configuration” ...

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... DS70293E-page 18 2.9 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect 10k resistor between V and the unused pins. © 2011 Microchip Technology Inc. SS ...

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... Overhead-free, single-cycle program loop constructs are supported using the REPEAT instruction, which is interruptible at any point. © 2011 Microchip Technology Inc. The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can serve as a data, and address or address offset register ...

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... X Data Bus Data Latch PCH PCL X RAM Address Loop Control Latch Logic 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg Multiplier Register Array Divide Support DMA 16 RAM DMA Controller 16-bit ALU 16 To Peripheral Modules © 2011 Microchip Technology Inc. ...

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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 3-2: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 PROGRAMMER’S MODEL PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG — — — — — — SRH © 2011 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12 W13 W14/Frame Pointer ...

Page 22

... The IPL<2:0> Status bits are read only when the NSTDIS bit (INTCON1<15> DS70293E-page 22 U-0 U-0 — — (2) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (2) U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2011 Microchip Technology Inc. ...

Page 23

... Program space visible in data space 0 = Program space not visible in data space bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — ...

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... The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of ‘0’ does not modify the operand. © 2011 Microchip Technology Inc. ...

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... Reserved Device Configuration Registers Reserved DEVID (2) Reserved Note: Memory areas are not shown to scale. © 2011 Microchip Technology Inc. 4.1 Program Address Space The program PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices is 4M instructions. and The space is addressable by a 24-bit value derived ...

Page 26

... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Table”. least significant word Instruction Width Section 7.1 “Interrupt Vector PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2011 Microchip Technology Inc. ...

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... Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2011 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code ...

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... X Data Unimplemented (X) DMA RAM can be used for general purpose data storage if the DMA function is not required in an application. LSb Address 0x0000 0x07FE 0x0800 6 Kbyte Near Data Space 0x13FE 0x1400 0x17FE 0x1800 0x8000 0xFFFE © 2011 Microchip Technology Inc. ...

Page 29

... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 4-4: DATA MEMORY MAP FOR PIC24HJ128GP202/204, PIC24HJ64GP202/204, PIC24HJ128GP502/504 AND PIC24HJ64GP502/504 DEVICES WITH 8 KB RAM MSb Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 8 Kbyte SRAM Space 0x1FFF 0x2001 0x27FF 0x2801 0x8001 Optionally Mapped into Program Memory 0xFFFF © ...

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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 ...

Page 31

TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ128GP202/502, PIC24HJ64GP202/502 AND PIC24HJ32GP302 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 CN30IE CN29IE — — CNPU1 0068 CN15PUE CN14PUE CN13PUE ...

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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr — — — INTCON1 0080 NSTDIS INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF ...

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TABLE 4-5: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...

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TABLE 4-7: OUTPUT COMPARE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS 018C ...

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TABLE 4-10: UART2 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U2MODE 0230 UARTEN — USIDL IREN U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — U2TXREG 0234 — — — — U2RXREG 0236 — — — ...

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TABLE 4-13: ADC1 REGISTER MAP FOR PIC24HJ64GP202/502, PIC24HJ128GP202/502 AND PIC24HJ32GP302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 AD1CON1 0320 ADON — ADSIDL ADDMABM AD1CON2 0322 VCFG<2:0> — AD1CON3 0324 ADRC — — AD1CHS123 0326 ...

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TABLE 4-15: DMA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA0CON 0380 CHEN SIZE DIR HALF DMA0REQ 0382 FORCE — — — DMA0STA 0384 DMA0STB 0386 DMA0PAD 0388 DMA0CNT 038A — — — — ...

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TABLE 4-15: DMA REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA5PAD 03C4 DMA5CNT 03C6 — — — — DMA6CON 03C8 CHEN SIZE DIR HALF DMA6REQ 03CA FORCE — — — DMA6STA 03CC DMA6STB ...

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... TABLE 4-16: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = (FOR PIC24HJ128GP502/504 AND PIC24HJ64GP502/504) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1CTRL1 0400 — — CSIDL ABAT C1CTRL2 0402 — — — C1VEC 0404 — — — C1FCTRL 0406 DMABS<2:0> C1FIFO 0408 — — ...

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... TABLE 4-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (FOR PIC24HJ128GP502/504 AND PIC24HJ64GP502/504) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0400- 041E C1BUFPNT1 0420 F3BP<3:0> C1BUFPNT2 0422 F7BP<3:0> C1BUFPNT3 0424 F11BP<3:0> C1BUFPNT4 0426 F15BP<3:0> C1RXM0SID 0430 C1RXM0EID 0432 C1RXM1SID 0434 C1RXM1EID 0436 C1RXM2SID ...

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... TABLE 4-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (FOR PIC24HJ128GP502/504 AND PIC24HJ64GP502/504) (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1RXF11SID 046C C1RXF11EID 046E C1RXF12SID 0470 C1RXF12EID 0472 C1RXF13SID 0474 C1RXF13EID 0476 C1RXF14SID 0478 C1RXF14EID 047A C1RXF15SID 047C C1RXF15EID 047E Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. ...

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TABLE 4-20: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ128GP202/502, PIC24HJ64GP202/502 AND PIC24HJ32GP302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RPOR0 06C0 — — — RPOR1 06C2 — — — RPOR2 06C4 — — — RPOR3 ...

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TABLE 4-22: PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR PIC24HPIC24HJ128GP202/502, PIC24HJ64GP202/502 AND PIC24HJ32GP302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 PMCON 0600 PMPEN — PSIDL ADRMUX<1:0> PMMODE 0602 BUSY IRQM<1:0> PMADDR ADDR15 CS1 0604 PMDOUT1 PMDOUT2 0606 ...

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TABLE 4-24: REAL-TIME CLOCK AND CALENDAR REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ALRMVAL 0620 ALCFGRPT 0622 ALRMEN CHIME RTCVAL 0624 RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC PADCFG1 02FC — — — Legend: ...

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TABLE 4-28: PORTA REGISTER MAP FOR PIC24HJ128GP204/504, PIC24HJ64GP204/504 AND PIC24HJ32GP304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISA 02C0 — — — — PORTA 02C2 — — — — LATA 02C4 — — — — ODCA ...

Page 46

TABLE 4-32: SECURITY REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 BSRAM 0750 — — — — SSRAM 0752 — — — — Legend unknown value on Reset, — = unimplemented, read as ...

Page 47

... Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2011 Microchip Technology Inc. 4.2.7 DATA RAM PROTECTION FEATURE The PIC24H product family supports Data RAM protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security ...

Page 48

... DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. © 2011 Microchip Technology Inc. ...

Page 49

... Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. © 2011 Microchip Technology Inc. 4.4.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program ...

Page 50

... Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. DS70293E-page 50 Program Counter 0 23 bits 1/0 TBLPAG 8 bits 24 bits Select 1 0 PSVPAG 8 bits 23 bits 0 EA 1/0 16 bits bits Byte Select © 2011 Microchip Technology Inc. ...

Page 51

... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2011 Microchip Technology Inc Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘ ...

Page 52

... PSV Area 0x800000 1111’ or and MOV.D instructions 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This 0xFFFF corresponds exactly to the same lower 15 bits of the actual program space address. © 2011 Microchip Technology Inc. ...

Page 53

... Program Counter Using 1/0 Table Instruction User/Configuration Space Select © 2011 Microchip Technology Inc. PGEC2/PGED2 or PGEC3/PGED3), and three other lines for power (V (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the and microcontroller just before shipping the product. This ...

Page 54

... Equation 5-2. MINIMUM ROW WRITE TIME 11064 Cycles = × × 0.05 1 0.00375 – Equation 5-3. MAXIMUM ROW WRITE TIME 11064 Cycles = × × – – 1 0.05 1 0.00375 (Register 5-1) controls which 5- write-only register that is for further © 2011 Microchip Technology Inc. ...

Page 55

... Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on a POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2011 Microchip Technology Inc. (1) U-0 U-0 — — (1) U-0 R/W-0 — ...

Page 56

... NVMKEY<7:0>: Key Register (write-only) bits DS70293E-page 56 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 57

... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2011 Microchip Technology Inc. 4. Write the first 64 instructions from data RAM into the program memory buffers (see 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit ...

Page 58

... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted © 2011 Microchip Technology Inc. ...

Page 59

... Regulator V DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2011 Microchip Technology Inc. A simplified block diagram of the Reset module is shown in Figure Any active source of reset will make the SYSRST signal active. On system Reset, some of the registers and associated with the CPU and peripherals are forced to ...

Page 60

... SWDTEN bit setting. DS70293E-page 60 (1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) U-0 R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 61

... All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2011 Microchip Technology Inc. (1) (CONTINUED) DS70293E-page 61 ...

Page 62

... T T OST LOCK T T OST LOCK — T LOCK T — OST — — Total Delay T OSCD OSCD LOCK OSCD OST OSCD OST — OSCD OST LOCK OSCD OST LOCK T LOCK OSCD OST T OSCD = 102.4 μs for a OST © 2011 Microchip Technology Inc. ...

Page 63

... GOTO instruction at the reset address, which redirects program execution to the appropriate start-up routine. 6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay T © 2011 Microchip Technology Inc. Vbor V BOR ...

Page 64

... The BOR cir- crosses V DD has elapsed. The delay BOR ) is programmed by PWRT Reset Timer Value Select register Section 25.0 “Special Features” initiated each time V BOR PWRT trip point BOR © 2011 Microchip Technology Inc. BOR bits DD ...

Page 65

... Reset state. This Reset state will not re- initialize the clock. The clock source in effect prior to the RESET instruction will remain. SYSRST is released at the next instruction cycle, and the reset vector fetch will commence. © 2011 Microchip Technology Inc BOR PWRT ...

Page 66

... RCON register value after a device Reset will be meaningful. Cleared by: POR, BOR POR, BOR POR, BOR POR POR, BOR PWRSAV instruction, CLRWDT instruction, POR, BOR POR, BOR POR, BOR — — © 2011 Microchip Technology Inc. ...

Page 67

... Fixed priority within a specified user priority level • Alternate Interrupt Vector Table (AIVT) for debug support • Fixed interrupt entry and return latencies © 2011 Microchip Technology Inc. 7.1 Interrupt Vector Table The Interrupt Vector Table (IVT), shown in resides in program memory, starting at location 000004h ...

Page 68

... Table 7-1 for the list of implemented interrupt vectors. DS70293E-page 68 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 (1) (1) © 2011 Microchip Technology Inc. ...

Page 69

... Microchip Technology Inc. AIVT Address 0x000104 Reserved 0x000106 Oscillator Failure 0x000108 Address Error 0x00010A Stack Error 0x00010C Math Error 0x00010E DMA Error 0x000110 Reserved 0x000112 Reserved 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – ...

Page 70

... DMA6 – DMA Channel 6 0x00019E DMA7 – DMA Channel 7 0x0001A0 C1TX – ECAN1 TX Data Request 0x0001A2 Reserved 0x0001A4 Reserved 0x0001A6 Reserved 0x0001A8 Reserved 0x0001AA Reserved 0x0001AC Reserved 0x0001AE Reserved 0x0001B0 Reserved 0x0001B2 Reserved 0x0001B4-0x0001FE Reserved Interrupt Source © 2011 Microchip Technology Inc. ...

Page 71

... IECx The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2011 Microchip Technology Inc. 7.3.4 IPCx The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels ...

Page 72

... Value at POR U = Unimplemented bit, read as ‘0’ (2) Register 3-2. U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit 0 U-0 U-0 U-0 — — — bit 8 R/W-0 U-0 U-0 PSV — — bit 0 ‘1’ = Bit is set © 2011 Microchip Technology Inc. ...

Page 73

... Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...

Page 74

... Interrupt on positive edge DS70293E-page 74 U-0 U-0 U-0 — — — U-0 U-0 R/W-0 — — INT2EP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 INT1EP INT0EP bit Bit is unknown ...

Page 75

... DMA0IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF ...

Page 76

... Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70293E-page 76 © 2011 Microchip Technology Inc. ...

Page 77

... INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF ...

Page 78

... MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70293E-page 78 © 2011 Microchip Technology Inc. ...

Page 79

... Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: Interrupts disabled on devices without ECAN™ modules. © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — ...

Page 80

... Unimplemented: Read as ‘0’ DS70293E-page 80 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown ...

Page 81

... U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ Note 1: Interrupts disabled on devices without ECAN™ modules. © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...

Page 82

... Interrupt request not enabled DS70293E-page 82 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE R/W-0 R/W-0 R/W-0 DMA0IE T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1EIE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 83

... Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Flag Status bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. DS70293E-page 83 ...

Page 84

... Interrupt request not enabled DS70293E-page 84 R/W-0 R/W-0 R/W-0 T5IE T4IE OC4IE R/W-0 R/W-0 R/W-0 INT1IE CNIE CMIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC3IE DMA2IE bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 85

... Interrupt request enabled 0 = Interrupt request not enabled bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. DS70293E-page 85 ...

Page 86

... DS70293E-page 86 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (1) (1) DMA3IE C1IE C1RXIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) U-0 U-0 — — bit 8 R/W-0 R/W-0 SPI2IE SPI2EIE bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 87

... Interrupt request enabled 0 = Interrupt request not enabled bit 13 DMA5IE: DMA Channel 5 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 ...

Page 88

... Interrupts disabled on devices without ECAN™ modules. DS70293E-page 88 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 DMA6IE CRCIE U2EIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 — — bit 8 R/W-0 U-0 U1EIE — bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 89

... Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...

Page 90

... Interrupt is priority 1 000 = Interrupt source is disabled DS70293E-page 90 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC2IP<2:0> bit 8 R/W-0 R/W-0 DMA0IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 91

... Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...

Page 92

... Interrupt is priority 1 000 = Interrupt source is disabled DS70293E-page 92 U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 DMA1IP<2:0> bit 8 R/W-0 R/W-0 U1TXIP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 93

... Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

Page 94

... Interrupt is priority 1 000 = Interrupt source is disabled DS70293E-page 94 R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 IC7IP<2:0> bit 8 R/W-0 R/W-0 INT1IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 95

... Unimplemented: Read as ‘0’ bit 2-0 DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

Page 96

... Interrupt is priority 1 000 = Interrupt source is disabled DS70293E-page 96 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U2RXIP<2:0> bit 8 R/W-0 R/W-0 T5IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 97

... SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Note 1: Interrupts disabled on devices without ECAN™ modules. © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 (1) — R/W-0 U-0 R/W-1 — ...

Page 98

... Interrupt source is disabled DS70293E-page 98 U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 DMA3IP<2:0> bit Bit is unknown ...

Page 99

... PMPIP<2:0>: Parallel Master Port Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — ...

Page 100

... Unimplemented: Read as ‘0’ DS70293E-page 100 U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RTCIP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 101

... U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — ...

Page 102

... Interrupts disabled on devices without ECAN™ modules. DS70293E-page 102 U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 (1) C1TXIP<2:0> bit 8 R/W-0 R/W-0 DMA6IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 103

... Unimplemented: Read as ‘0’ bit 6-0 VECNUM: Vector Number of Pending Interrupt bits 0111111 = Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 © 2011 Microchip Technology Inc. U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM< ...

Page 104

... Only user interrupts with a priority level lower can be disabled. Trap sources (level 8-level 15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. © 2011 Microchip Technology Inc. ...

Page 105

... SPI2 – Transfer Done ECAN1 – RX Data Ready PMP – Master Data Transfer ECAN1 – TX Data Request © 2011 Microchip Technology Inc. Direct Memory Access (DMA very efficient mechanism of copying data between peripheral SFRs (e.g., UART Receive register, Input Capture 1 buffer), ...

Page 106

... Alternatively, an interrupt can be generated when half of the block has been filled. Peripheral Indirect Address DMA Controller DMA Channels DMA DS Bus DMA Ready Peripheral 3 CPU DMA CPU DMA CPU DMA DMA DMA Ready Ready Peripheral 2 Peripheral 1 © 2011 Microchip Technology Inc. ...

Page 107

... DMACS1, are common to all DMAC channels. DMACS0 contains the DMA RAM and SFR write collision flags, XWCOLx and PWCOLx, respectively. DMACS1 indicates DMA channel and Ping-Pong mode status. © 2011 Microchip Technology Inc. The DMAxCON, DMAxREQ, DMAxPAD DMAxCNT are all conventional read/write registers. ...

Page 108

... Continuous, Ping-Pong modes disabled DS70293E-page 108 R/W-0 R/W-0 HALF NULLW R/W-0 U-0 AMODE<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 R/W-0 — MODE<1:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 109

... The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced DMA transfer is complete. 2: Refer to Table 7-1 for a complete listing of IRQ numbers for all interrupt sources. © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — ...

Page 110

... Bit is cleared R/W-0 R/W-0 R/W-0 STB<15:8> R/W-0 R/W-0 R/W-0 STB<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 111

... CNT<9:0>: DMA Transfer Count Register bits Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. 2: Number of DMA transfers = CNT<9:0> © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PAD<15:8> R/W-0 R/W-0 R/W-0 PAD< ...

Page 112

... R/C-0 R/C-0 R/C-0 PWCOL4 PWCOL3 PWCOL2 R/C-0 R/C-0 R/C-0 XWCOL4 XWCOL3 XWCOL2 C = Clear only bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/C-0 R/C-0 PWCOL1 PWCOL0 bit 8 R/C-0 R/C-0 XWCOL1 XWCOL0 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 113

... Write collision detected write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected © 2011 Microchip Technology Inc. DS70293E-page 113 ...

Page 114

... DMA0STB register selected 0 = DMA0STA register selected DS70293E-page 114 U-0 R-1 R-1 — LSTCH<3:0> R-0 R-0 R-0 PPST4 PPST3 PPST2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-1 R-1 bit 8 R-0 R-0 PPST1 PPST0 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 115

... R-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits © 2011 Microchip Technology Inc. R-0 R-0 R-0 DSADR<15:8> R-0 R-0 R-0 DSADR<7:0> Unimplemented bit, read as ‘0’ ...

Page 116

... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293E-page 116 © 2011 Microchip Technology Inc. ...

Page 117

... F P document F and F are used interchangeably, except in the case of Doze mode mode is used in any ratio other than 1:1, which is the default. © 2011 Microchip Technology Inc. The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 provides: • External and internal oscillator options as clock sources and • ...

Page 118

... MHz are supported by the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 architecture. Instruction execution speed or device operating frequency EQUATION 9-1: described in Section 25.1 “Configuration Configuration bits, FNOSC<2:0> bits, POSCMD<1:0> Table 9-1. is divided OSC ) and the defines the given by: DEVICE OPERATING FREQUENCY F OSC F = ------------- CY 2 © 2011 Microchip Technology Inc. ...

Page 119

... BLOCK DIAGRAM Source (Crystal, External Clock or Internal RC) Note 1: This frequency range must be satisfied at all times. © 2011 Microchip Technology Inc. For a primary oscillator or FRC oscillator, output ‘F the PLL output ‘F EQUATION 9-2: For example, suppose a 10 MHz crystal is being used with the selected oscillator mode of XT with PLL. • ...

Page 120

... DS70293E-page 120 Oscillator Source POSCMD<1:0> Internal xx Internal xx Internal xx ) Secondary xx Primary 10 Primary 01 Primary 00 Primary 10 Primary 01 Primary 00 Internal xx Internal xx See FNOSC<2:0> Note 1, 2 111 1 110 1 101 1 100 — 011 — 011 1 011 — 010 — 010 1 010 1 001 1 000 © 2011 Microchip Technology Inc. ...

Page 121

... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: This register is reset only on a Power-on Reset (POR). © 2011 Microchip Technology Inc. (1,3) R-0 U-0 R/W-y — ...

Page 122

... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: This register is reset only on a Power-on Reset (POR). DS70293E-page 122 (1,3) (CONTINUED) © 2011 Microchip Technology Inc. ...

Page 123

... Input/33 • • • 00001 = Input/3 00000 = Input/2 (default) Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. 2: This register is reset only on a Power-on Reset (POR). © 2011 Microchip Technology Inc. (2) R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE< ...

Page 124

... This register is reset only on a Power-on Reset (POR). DS70293E-page 124 (1) U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-0 — PLLDIV<8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 125

... OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. 2: This register is reset only on a Power-on Reset (POR). © 2011 Microchip Technology Inc. (2) U-0 U-0 U-0 — ...

Page 126

... In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. to Section 39. “Oscillator (Part III)” (DS70308) in the “dsPIC33F/ PIC24H Family Reference Manual” for details. © 2011 Microchip Technology Inc. ...

Page 127

... Configuration”. EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2011 Microchip Technology Inc. 10.2 Instruction-Based Power-Saving Modes PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices have two special and ...

Page 128

... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control regis- ters are already configured to enable module operation). There are eight possible © 2011 Microchip Technology Inc. ...

Page 129

... Unimplemented: Read as ‘0’ bit 1 C1MD: ECAN1 Module Disable bit 1 = ECAN1 module is disabled 0 = ECAN1 module is enabled bit 0 AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled © 2011 Microchip Technology Inc. R/W-0 R/W-0 U-0 T2MD T1MD — R/W-0 R/W-0 ...

Page 130

... Output Compare 1 module is enabled DS70293E-page 130 U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — OC4MD OC3MD U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 IC2MD IC1MD bit 8 R/W-0 R/W-0 OC2MD OC1MD bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 131

... CRCMD: CRC Module Disable bit 1 = CRC module is disabled 0 = CRC module is enabled bit 6 DAC1MD: DAC1 Module Disable bit 1 = DAC1 module is disabled 0 = DAC1 module is enabled bit 5-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 R/W-0 — — CMPMD U-0 U-0 U-0 — ...

Page 132

... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293E-page 132 © 2011 Microchip Technology Inc. ...

Page 133

... WR Port Data Latch Read LAT Read Port © 2011 Microchip Technology Inc. has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through”, in which a port’s digital output can drive the input of a peripheral that shares the same pin. ...

Page 134

... CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. Example 11-1. © 2011 Microchip Technology Inc. ...

Page 135

... The association of a peripheral to a peripheral select- able pin is handled in two different ways, depending on whether an input or output is being mapped. © 2011 Microchip Technology Inc. 11.6.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it is mapped to ...

Page 136

... SCK1 RPINR20 SS1 RPINR21 SDI2 RPINR22 SCK2 RPINR22 SS2 RPINR23 CIRX RPINR26 (1) Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> T4CKR<4:0> T5CKR<4:0> IC1R<4:0> IC2R<4:0> IC7R<4:0> IC8R<4:0> OCFAR<4:0> U1RXR<4:0> U1CTSR<4:0> U2RXR<4:0> U2CTSR<4:0> SDI1R<4:0> SCK1R<4:0> SS1R<4:0> SDI2R<4:0> SCK2R<4:0> SS2R<4:0> CIRXR<4:0> © 2011 Microchip Technology Inc. ...

Page 137

... SDO1 SCK1 SS1 SDO2 SCK2 SS2 C1TX OC1 OC2 OC3 OC4 © 2011 Microchip Technology Inc. FIGURE 11-3: U1TX Output enable 11-27). The U1RTS Output enable 4 OC4 Output U1TX Output U1RTS Output 4 OC4 Output RPn tied to default port pin 00000 RPn tied to Comparator1 Output ...

Page 138

... Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows user applications unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. built-in C © 2011 Microchip Technology Inc. ...

Page 139

... INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. of devices IOLOCK bit to ‘0’. See Register R/W-1 R/W-1 INT1R< ...

Page 140

... Input tied to RP1 00000 = Input tied to RP0 DS70293E-page 140 U-0 U-0 — — R/W-1 R/W-1 INT2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 141

... T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 T2CKR<4:0> Unimplemented bit, read as ‘0’ ...

Page 142

... Input tied to RP1 00000 = Input tied to RP0 DS70293E-page 142 R/W-1 R/W-1 T5CKR<4:0> R/W-1 R/W-1 T4CKR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 143

... IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 IC1R<4:0> Unimplemented bit, read as ‘0’ ...

Page 144

... Input tied to RP1 00000 = Input tied to RP0 DS70293E-page 144 R/W-1 R/W-1 IC8R<4:0> R/W-1 R/W-1 IC7R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 145

... OCFAR<4:0>: Assign Output Compare A (OCFA) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 OCFAR<4:0> Unimplemented bit, read as ‘0’ ...

Page 146

... Input tied to RP1 00000 = Input tied to RP0 DS70293E-page 146 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 U1RXR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 147

... U2RXR<4:0>: Assign UART2 Receive (U2RX) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 U2CTSR<4:0> R/W-1 R/W-1 U2RXR<4:0> Unimplemented bit, read as ‘0’ ...

Page 148

... Input tied to RP1 00000 = Input tied to RP0 DS70293E-page 148 R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 SDI1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 149

... SS1R<4:0>: Assign SPI1 Slave Select Input (SS1) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 SS1R<4:0> ...

Page 150

... Input tied to RP1 00000 = Input tied to RP0 DS70293E-page 150 R/W-1 R/W-1 SCK2R<4:0> R/W-1 R/W-1 SDI2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 151

... Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 Note 1: This register is disabled on devices without ECAN™ modules. © 2011 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 SS2R<4:0> Unimplemented bit, read as ‘0’ ...

Page 152

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for © 2011 Microchip Technology Inc. ...

Page 153

... RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see peripheral function numbers) © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP5R<4:0> R/W-0 R/W-0 R/W-0 RP4R< ...

Page 154

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for © 2011 Microchip Technology Inc. ...

Page 155

... RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see peripheral function numbers) © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP13R<4:0> R/W-0 R/W-0 R/W-0 RP12R< ...

Page 156

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for © 2011 Microchip Technology Inc. ...

Page 157

... Unimplemented: Read as ‘0’ bit 4-0 RP22R<4:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits (see peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP21R<4:0> R/W-0 R/W-0 R/W-0 RP20R< ...

Page 158

... This register is implemented in 44-pin devices only. DS70293E-page 158 R/W-0 R/W-0 R/W-0 RP25R<4:0> R/W-0 R/W-0 R/W-0 RP24R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for © 2011 Microchip Technology Inc. ...

Page 159

... TCKPS<1:0> SOSCI (1) LPOSCEN Note 1: Refer to Section 9.0 “Oscillator Configuration” © 2011 Microchip Technology Inc. The unique features of Timer1 allow used for Real Time Clock (RTC) applications. A block diagram of Timer1 is shown in The Timer1 module can operate in one of the following and modes: ...

Page 160

... Unimplemented: Read as ‘0’ DS70293E-page 160 U-0 U-0 — — R/W-0 U-0 TCKPS<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TSYNC TCS — bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 161

... CY TCKPS<1:0> Prescaler Sync TxCK TCKPS<1:0> © 2011 Microchip Technology Inc. • A Type B timer can be concatenated with a Type C timer to form a 32-bit timer • The external clock input (TxCK) is always synchronized to the internal device clock and the clock synchronization is performed after the prescaler ...

Page 162

... The timer value at any point is stored in the register pair, TMR3:TMR2 or TMR5:TMR4, which always contains the most significant word of the count, while TMR2 or TMR4 contains the least significant word. Table 13-2. 32-BIT TIMER TYPE C Timer (msw) Timer3 Timer5 13-3. The 32-timer module can © 2011 Microchip Technology Inc. ...

Page 163

... F CY (/n) TCKPS<1:0> Prescaler Sync (/n) TxCK TCKPS<1:0> Note 1: ADC trigger is available only on TMR3:TMR2 and TMR5:TMR2 32-bit timers. 2: Timer Type B Timer ( and 4). 3: Timer Type C Timer ( and 5). © 2011 Microchip Technology Inc. Falling Edge Detect PRy PRx Comparator 10 lsw TMRx TMRy 00 x1 TMRyHLD ...

Page 164

... Unimplemented: Read as ‘0’ DS70293E-page 164 U-0 U-0 — — R/W-0 R/W-0 TCKPS<1:0> T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 165

... When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>) , the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), these bits have no effect. © 2011 Microchip Technology Inc. U-0 U-0 (1) — ...

Page 166

... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293E-page 166 © 2011 Microchip Technology Inc. ...

Page 167

... Mode Sleep/Idle Wake-up Mode Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2011 Microchip Technology Inc. • Simple Capture Event modes: - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of ...

Page 168

... Input capture module turned off DS70293E-page 168 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE HC = Cleared in Hardware U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 169

... TMR3 TMR2 © 2011 Microchip Technology Inc. The Output Compare module can select either Timer2 or Timer3 for its time base. The module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. and The state of the output pin changes when the timer ...

Page 170

... OCx Falling edge 1 Current output is maintained OCx Rising and Falling edge OCx Falling edge 0 OCx Falling edge OCxR is zero No interrupt 1, if OCxR is non-zero OCFA Falling edge for OC1 to OC4 1, if OCxR is non-zero Timer is reset on period match — © 2011 Microchip Technology Inc. ...

Page 171

... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2011 Microchip Technology Inc. U-0 U-0 U-0 — ...

Page 172

... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293E-page 172 © 2011 Microchip Technology Inc. ...

Page 173

... SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF © 2011 Microchip Technology Inc. The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices can be serial EEPROMs, shift registers, display drivers, analog-to-digital converters, etc ...

Page 174

... Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. DS70293E-page 174 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R-0 R-0 SPITBF SPIRBF bit Bit is unknown ...

Page 175

... The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1 not set both Primary and Secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1. © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 DISSCK DISSDO ...

Page 176

... The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1 not set both Primary and Secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1. DS70293E-page 176 (2) (2) © 2011 Microchip Technology Inc. ...

Page 177

... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application © 2011 Microchip Technology Inc. U-0 U-0 U-0 — ...

Page 178

... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293E-page 178 © 2011 Microchip Technology Inc. ...

Page 179

... I C supports multi-master operation, detects bus collision and arbitrates accordingly © 2011 Microchip Technology Inc. 17.1 Operating Modes The hardware fully implements all the master and slave functions of the I specifications, as well as 7-bit and 10-bit addressing. ...

Page 180

... Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2011 Microchip Technology Inc. ...

Page 181

... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2011 Microchip Technology Inc. R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...

Page 182

... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence 0 = Start condition not in progress DS70293E-page 182 2 C master, applicable during master receive) C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte 2 C master master master) © 2011 Microchip Technology Inc. ...

Page 183

... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2011 Microchip Technology Inc. U-0 U-0 — — R/C-0 HSC ...

Page 184

... Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70293E-page 184 2 C slave device address byte. © 2011 Microchip Technology Inc. ...

Page 185

... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2011 Microchip Technology Inc. U-0 U-0 U-0 — ...

Page 186

... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293E-page 186 © 2011 Microchip Technology Inc. ...

Page 187

... Note 1: Both UART1 and UART2 can trigger a DMA data transfer DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word (i.e., UTXISEL<1:0> and URXISEL<1:0> = 00). © 2011 Microchip Technology Inc. The primary features of the UART module are: • Full-Duplex 9-bit Data Transmission through the UxTX and UxRX pins • ...

Page 188

... DS70293E-page 188 MODE REGISTER x R/W-0 R/W-0 U-0 (2) IREN RTSMD R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) R/W-0 R/W-0 — UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 189

... Refer to Section 17. “UART” (DS70232) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2011 Microchip Technology Inc. MODE REGISTER (CONTINUED) x DS70293E-page 189 ...

Page 190

... U-0 R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R-0 R-1 (1) UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Clear only bit x = Bit is unknown © 2011 Microchip Technology Inc. ...

Page 191

... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 17. “UART” (DS70232) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation. © 2011 Microchip Technology Inc. STATUS AND CONTROL REGISTER (CONTINUED) x DS70293E-page 191 ...

Page 192

... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293E-page 192 © 2011 Microchip Technology Inc. ...

Page 193

... Three full acceptance filter masks • DeviceNet™ addressing support • Programmable wake-up functionality with integrated low-pass filter © 2011 Microchip Technology Inc. • Programmable Loopback mode supports self-test operation • Signaling via interrupt capabilities for all CAN receiver and transmitter error states • ...

Page 194

... RxF11 Filter RxF10 Filter RxF9 Filter RxF8 Filter RxF7 Filter RxF6 Filter RxF5 Filter RxF4 Filter RxF3 Filter RxF2 Filter RxF1 Filter RxF0 Filter Buffer RxM2 Mask RxM1 Mask RxM0 Mask Control CPU Configuration Bus Logic Interrupts © 2011 Microchip Technology Inc. ...

Page 195

... Module Disable mode. The I/O pins reverts to normal I/O function when the module is in the Module Disable mode. © 2011 Microchip Technology Inc. The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2< ...

Page 196

... Use buffer window DS70293E-page 196 R/W-0 r-0 R/W-1 ABAT — U-0 R/W-0 U-0 — CANCAP — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 REQOP<2:0> bit 8 U-0 R/W-0 — WIN bit Bit is unknown © 2011 Microchip Technology Inc. ...

Page 197

... DNCNT<4:0>: DeviceNet™ Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compare up to data byte 3, bit 6 with EID<17> • • • 00001 = Compare up to data byte 1, bit 7 with EID<0> 00000 = Do not compare data bytes © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R-0 ...

Page 198

... TRB2 buffer interrupt 0000001 = TRB1 buffer interrupt 0000000 = TRB0 Buffer interrupt DS70293E-page 198 R-0 R-0 R-0 FILHIT<4:0> R-0 R-0 R-0 ICODE<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...

Page 199

... FSA<4:0>: FIFO Area Starts with Buffer bits 11111 = Read buffer RB31 11110 = Read buffer RB30 • • • 00001 = TX/RX buffer TRB1 00000 = TX/RX buffer TRB0 © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 FSA< ...

Page 200

... TRB1 buffer 000000 = TRB0 buffer DS70293E-page 200 R-0 R-0 R-0 FBP<5:0> R-0 R-0 R-0 FNRB<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...

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