IC DSPIC MCU/DSP 128K 64TQFP

DSPIC33FJ128GP306-I/PT

Manufacturer Part NumberDSPIC33FJ128GP306-I/PT
DescriptionIC DSPIC MCU/DSP 128K 64TQFP
ManufacturerMicrochip Technology
SeriesdsPIC™ 33F
DSPIC33FJ128GP306-I/PT datasheets
 

Specifications of DSPIC33FJ128GP306-I/PT

Program Memory TypeFLASHProgram Memory Size128KB (128K x 8)
Package / Case64-TFQFPCore ProcessordsPIC
Core Size16-BitSpeed40 MIPs
ConnectivityI²C, IrDA, LIN, SPI, UART/USARTPeripheralsAC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o53Ram Size16K x 8
Voltage - Supply (vcc/vdd)3 V ~ 3.6 VData ConvertersA/D 18x10b/12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
ProductDSCsData Bus Width16 bit
Processor SeriesDSPIC33FCoredsPIC
Maximum Clock Frequency40 MHzNumber Of Programmable I/os53
Data Ram Size16 KBMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By SupplierPG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033Minimum Operating Temperature- 40 C
Package64TQFPDevice CoredsPIC
Family NamedSPIC33Maximum Speed40 MHz
Operating Supply Voltage3.3 VInterface TypeI2C/SPI/UART
On-chip Adc18-chx10-bit|18-chx12-bitNumber Of Timers9
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With876-1001 - DSPIC33 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
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6.5
Fail-Safe Clock Monitor (FSCM)
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
system clock over to the FRC oscillator. The application
program then can either attempt to restart the oscillator,
or execute a controlled shutdown. The trap can be
treated as a warm Reset by simply loading the Reset
address into the oscillator fail trap vector.
© 2005 Microchip Technology Inc.
6.6
Reset System
The Reset system combines all Reset sources and
controls the device Master Reset signal.
Device Reset sources include:
• POR: Power-on Reset
• BOR: Brown-out Reset
• SWR: RESET Instruction
• EXTR: MCLR Reset
• WDTR: Watchdog Timer Time-out Reset
• TRAPR: Trap Conflict
• IOPUWR: Attempted execution of an Illegal
Opcode, or Indirect Addressing, using an
Uninitialized W register
Preliminary
dsPIC33F
DS70155C-page 21