DSPIC33FJ128GP306A-I/PT Microchip Technology, DSPIC33FJ128GP306A-I/PT Datasheet
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DSPIC33FJ128GP306A-I/PT Summary of contents
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... Microchip Technology Inc. High-Performance , 16-bit Digital Signal Controllers Data Sheet DS70593C ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... available interrupt sources • five external interrupts • Seven programmable priority levels • Five processor exceptions © 2011 Microchip Technology Inc. dsPIC33FJXXXGPX06A/X08A/X10A Digital I/O: • programmable digital I/O pins • Wake-up/Interrupt-on-Change pins • Output pins can drive from 3.0V to 3.6V • ...
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... Industrial and extended temperature • Low-power consumption Packaging: • 100-pin TQFP (14x14x1 mm and 12x12x1 mm) • 80-pin TQFP (12x12x1 mm) • 64-pin TQFP (10x10x1 mm) • 64-pin QFN (9x9x0.9 mm) Note: See the device variant tables for exact peripheral features per device. © 2011 Microchip Technology Inc. ...
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... Device Pins Memory (Kbyte) dsPIC33FJ64GP206A 64 64 dsPIC33FJ64GP306A 64 64 dsPIC33FJ64GP310A 100 64 dsPIC33FJ64GP706A 64 64 dsPIC33FJ64GP708A 80 64 dsPIC33FJ64GP710A 100 64 dsPIC33FJ128GP206A 64 128 dsPIC33FJ128GP306A 64 128 dsPIC33FJ128GP310A 100 128 dsPIC33FJ128GP706A 64 128 dsPIC33FJ128GP708A 80 128 dsPIC33FJ128GP710A 100 128 dsPIC33FJ256GP506A 64 256 dsPIC33FJ256GP510A 100 256 dsPIC33FJ256GP710A 100 256 Note 1: RAM size is inclusive of 2 Kbytes DMA RAM. ...
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... Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected to V externally. SS DS70593C-page dsPIC33FJ64GP206A dsPIC33FJ128GP206A Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 48 PGED2/SOSCI/T4CK/CN1/RC13 47 OC1/RD0 46 IC4/INT4/RD11 45 IC3/INT3/RD10 44 43 IC2/U1CTS/INT2/RD9 42 IC1/INT1/RD8 OSC2/CLKO/RC15 40 39 OSC1/CLKIN/RC12 SCL1/RG2 36 SDA1/RG3 35 U1RTS/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 U1TX/SDO1/RF3 © 2011 Microchip Technology Inc. ...
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... AN2/SS1/CN4/RB2 14 PGEC3/AN1/V -/CN3/RB1 15 REF PGED3/AN0/V +/CN2/RB0 16 REF Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected to V externally. SS © 2011 Microchip Technology Inc dsPIC33FJ64GP306A dsPIC33FJ128GP306A Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 48 PGED2/SOSCI/T4CK/CN1/RC13 47 OC1/RD0 46 IC4/INT4/RD11 45 IC3/INT3/RD10 44 IC2/U1CTS/INT2/RD9 43 IC1/INT1/RD8 42 ...
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... Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected to V externally. SS DS70593C-page dsPIC33FJ256GP506A Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 © 2011 Microchip Technology Inc. ...
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... AN5/IC8/CN7/RB5 12 AN4/IC7/CN6/RB4 13 AN3/CN5/RB3 14 AN2/SS1/CN4/RB2 15 PGEC3/AN1/V -/CN3/RB1 REF 16 PGED3/AN0/V +/CN2/RB0 REF Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected to V externally. SS © 2011 Microchip Technology Inc dsPIC33FJ64GP706A dsPIC33FJ128GP706A Pins are tolerant 48 PGEC2/SOSCO/T1CK/CN0/RC14 47 PGED2/SOSCI/T4CK/CN1/RC13 46 OC1/RD0 45 IC4/INT4/RD11 44 ...
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... SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGEC3/AN1/V -/CN3/RB1 15 REF PGED3/AN0/V +/CN2/RB0 16 REF DS70593C-page dsPIC33FJ64GP206A 41 40 dsPIC33FJ128GP206A Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 © 2011 Microchip Technology Inc. ...
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... SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGEC3/AN1/V -/CN3/RB1 15 REF PGED3/AN0/V +/CN2/RB0 16 REF © 2011 Microchip Technology Inc dsPIC33FJ64GP306A 41 dsPIC33FJ128GP306A Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 DS70593C-page 11 ...
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... SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGEC3/AN1/V -/CN3/RB1 15 REF PGED3/AN0/V +/CN2/RB0 16 REF DS70593C-page dsPIC33FJ256GP506A Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 © 2011 Microchip Technology Inc. ...
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... AN16/T2CK/T7CK/RC1 2 AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGEC3/AN1/V -/CN3/RB1 15 REF PGED3/AN0/V +/CN2/RB0 16 REF © 2011 Microchip Technology Inc dsPIC33FJ64GP706A 41 dsPIC33FJ128GP706A Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 ...
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... TMS/AN20/INT1/RA12 13 TDO/AN21/INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/CN4/RB2 18 PGEC3/AN1/CN3/RB1 19 PGED3/AN0/CN2/RB0 20 DS70593C-page 14 dsPIC33FJ64GP708A dsPIC33FJ128GP708A = Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 60 PGED2/SOSCI/CN1/RC13 59 58 OC1/RD0 57 IC4/RD11 56 IC3/RD10 55 IC2/RD9 IC1/RD8 54 SDA2/INT4/RA3 53 52 SCL2/INT3/RA2 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 SCL1/RG2 47 SDA1/RG3 46 45 SCK1/INT0/RF6 SDI1/RF7 44 43 SDO1/RF8 42 U1RX/RF2 U1TX/RF3 41 © 2011 Microchip Technology Inc. ...
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... AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 20 AN5/CN7/RB5 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGEC3/AN1/CN3/RB1 24 PGED3/AN0/CN2/RB0 25 © 2011 Microchip Technology Inc. dsPIC33FJ64GP310A dsPIC33FJ128GP310A = Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 73 PGED2/SOSCI/CN1/RC13 72 OC1/RD0 71 IC4/RD11 IC3/RD10 70 69 IC2/RD9 68 IC1/RD8 INT4/RA15 67 INT3/RA14 OSC2/CLKO/RC15 63 OSC1/CLKIN/RC12 TDO/RA5 60 TDI/RA4 ...
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... AN2/SS1/CN4/RB2 23 PGEC3/AN1/CN3/RB1 24 25 PGED3/AN0/CN2/RB0 DS70593C-page 16 dsPIC33FJ256GP510A = Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 73 PGED2/SOSCI/CN1/RC13 72 OC1/RD0 IC4/RD11 71 IC3/RD10 70 IC2/RD9 69 68 IC1/RD8 INT4/RA15 67 66 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 TDO/RA5 60 TDI/RA4 SDA2/RA3 59 58 SCL2/RA2 57 SCL1/RG2 SDA1/RG3 56 SCK1/INT0/RF6 55 54 SDI1/RF7 53 SDO1/RF8 U1RX/RF2 52 51 U1TX/RF3 © 2011 Microchip Technology Inc. ...
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... AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 AN5/CN7/RB5 20 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGEC3/AN1/CN3/RB1 24 PGED3/AN0/CN2/RB0 25 © 2011 Microchip Technology Inc. dsPIC33FJ64GP710A dsPIC33FJ128GP710A dsPIC33FJ256GP710A = Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 73 PGED2/SOSCI/CN1/RC13 OC1/RD0 72 71 IC4/RD11 70 IC3/RD10 IC2/RD9 69 68 IC1/RD8 INT4/RA15 67 66 INT3/RA14 OSC2/CLKO/RC15 63 OSC1/CLKIN/RC12 TDO/RA5 ...
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... Packaging Information.............................................................................................................................................................. 327 Appendix A: Migrating from dsPIC33FJXXXGPX06/X08/X10 Devices to dsPIC33FJXXXGPX06A/X08A/X10A Devices ................ 339 Appendix B: Revision History............................................................................................................................................................. 340 Index ................................................................................................................................................................................................. 343 The Microchip Web Site ..................................................................................................................................................................... 347 Customer Change Notification Service .............................................................................................................................................. 347 Customer Support .............................................................................................................................................................................. 347 Reader Response .............................................................................................................................................................................. 348 Product Identification System............................................................................................................................................................. 349 DS70593C-page 18 © 2011 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com © 2011 Microchip Technology Inc. to receive the most current information on all of our products. DS70593C-page 19 ...
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... NOTES: DS70593C-page 20 © 2011 Microchip Technology Inc. ...
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... This document contains device specific information for the following devices: • dsPIC33FJ64GP206A • dsPIC33FJ64GP306A • dsPIC33FJ64GP310A • dsPIC33FJ64GP706A • dsPIC33FJ64GP708A • dsPIC33FJ64GP710A • dsPIC33FJ128GP206A • dsPIC33FJ128GP306A • dsPIC33FJ128GP310A • dsPIC33FJ128GP706A • dsPIC33FJ128GP708A • dsPIC33FJ128GP710A • dsPIC33FJ256GP506A • dsPIC33FJ256GP510A • dsPIC33FJ256GP710A The ...
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... Instruction Reg DSP Engine Register Array Divide Support 16-bit ALU MCLR OC/ DCI ADC1,2 PWM1-8 CN1-23 SPI1,2 I2C1,2 PORTA DMA RAM PORTB DMA 16 Controller PORTC PORTD 16 PORTE 16 PORTF 16 PORTG 16 ECAN1,2 UART1,2 “Pin Diagrams” section for the © 2011 Microchip Technology Inc. ...
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... RF12-RF13 I/O ST Legend: CMOS = CMOS compatible input or output Schmitt Trigger input with CMOS levels; © 2011 Microchip Technology Inc. Description Analog input channels. Positive supply for analog modules. This pin must be connected at all times. Ground reference for analog modules. External clock source input. Always associated with OSC1 pin function. ...
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... Positive supply for peripheral logic and I/O pins. CPU logic flter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Analog = Analog input Output Power I = Input © 2011 Microchip Technology Inc. ...
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... Section 22. “Direct Memory Access (DMA)” (DS70182) • Section 23. “CodeGuard™ Security” (DS70199) • Section 24. “Programming and Diagnostics” (DS70207) • Section 25. “Device Configuration” (DS70194) • Section 26. “Development Tool Support” (DS70200) © 2011 Microchip Technology Inc. product page web site from ...
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... NOTES: DS70593C-page 26 © 2011 Microchip Technology Inc. ...
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... ADC module is implemented Note: The AV and AV pins must connected independent of the ADC voltage reference source. © 2011 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • ...
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... Overstress (EOS). Ensure that the MCLR pin Section 25 additional Section 22.2 and V ) and fast signal shown in Figure 2- Figure 2-2 within EXAMPLE OF MCLR PIN CONNECTIONS R R1 MCLR dsPIC33F JP C and V specifications are met and V specifications are met. IL © 2011 Microchip Technology Inc. ...
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... REAL ICE™ In-Circuit Emulator User’s Guide” DS51616 ® • “Using MPLAB REAL ICE™” (poster) DS51749 © 2011 Microchip Technology Inc. 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 “ ...
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... Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect 10k resistor between V and the unused pins. DS70593C-page 30 SS © 2011 Microchip Technology Inc. ...
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... The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred and Y data memory. Each memory block has its own indepen- © 2011 Microchip Technology Inc. dent Address Generation Unit (AGU). The MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear data space ...
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... Data Latch PCH PCL X RAM Y RAM Address Address Loop Latch Control Latch Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support DMA 16 RAM DMA Controller 16-bit ALU 16 To Peripheral Modules © 2011 Microchip Technology Inc. ...
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... Registers AD39 DSP AccA Accumulators AccB PC22 7 0 TBLPAG Data Table Page Address 7 0 PSVPAG 22 DOSTART OAB SAB DA SRH © 2011 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 0 ...
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... The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). DS70593C-page 34 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2011 Microchip Technology Inc. ...
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... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). © 2011 Microchip Technology Inc. (2) DS70593C-page 35 ...
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... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70593C-page 36 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set © 2011 Microchip Technology Inc. ...
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... W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. © 2011 Microchip Technology Inc. 3.6 DSP Engine The DSP ...
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... FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70593C-page 38 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2011 Microchip Technology Inc. ...
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... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter prior to accumulation. © 2011 Microchip Technology Inc. 3.6.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true, or complement data into the other input ...
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... Section 3.6.2.4 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator write-back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. © 2011 Microchip Technology Inc. (see ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2011 Microchip Technology Inc. 3.6.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... NOTES: DS70593C-page 42 © 2011 Microchip Technology Inc. ...
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... Reserved Device Configuration Registers Reserved DEVID (2) Note: Memory areas are not shown to scale. © 2011 Microchip Technology Inc. 4.1 Program Address Space The program address dsPIC33FJXXXGPX06A/X08A/X10A devices is 4M instructions. The space is addressable by a 24-bit value derived from either the 23-bit Program Counter ...
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... Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in “Interrupt Vector least significant word Instruction Width devices addresses between 0x00000 and devices also Section 7.1 Table”. PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2011 Microchip Technology Inc. ...
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... Data byte writes only write to the corresponding side of the array or register which matches the byte address. © 2011 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code ...
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... Memory 0xFFFF DS70593C-page 46 PIC33FJXXXGPX06A/X08A/X10A DEVICES WITH 8 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x17FE 0x1800 Y Data RAM (Y) 0x1FFE 0x2000 DMA RAM 0x27FE 0x2800 0x8000 X Data Unimplemented (X) 0xFFFE 8 Kbyte Near Data Space © 2011 Microchip Technology Inc. ...
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... Kbyte 0x2801 SRAM Space 0x3FFF 0x4001 0x47FF 0x4801 0x8001 Optionally Mapped into Program Memory 0xFFFF © 2011 Microchip Technology Inc. LSB Address 16 bits MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x1FFE 0x27FE 0x2800 Y Data RAM (Y) 0x3FFE ...
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... Optionally Mapped into Program Memory 0xFFFF DS70593C-page 48 LSB Address 16 bits MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x47FE 0x4800 Y Data RAM (Y) 0x77FE 0x7800 DMA RAM 0x7FFE 0x8000 X Data Unimplemented (X) 0xFFFE © 2011 Microchip Technology Inc. 8 Kbyte Near Data Space ...
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... All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. © 2011 Microchip Technology Inc. 4.2.6 DMA RAM Every dsPIC33FJXXXGPX06A/X08A/X10A contains 2 Kbytes of dual ported DMA RAM located at the end of Y data space ...
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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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TABLE 4-1: CPU CORE REGISTERS MAP (CONTINUED) SFR SFR Name Bit 15 Bit 14 Bit 13 Addr XBREV 0050 BREN DISICNT 0052 — — BSRAM 0750 — — — SSRAM 0752 — — — Legend unknown value on ...
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TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXXGPX10A DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 — — — — CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE ...
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TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF AD1IF U1TXIF IFS1 0086 ...
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TABLE 4-6: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 4-7: INPUT CAPTURE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ...
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TABLE 4-8: OUTPUT COMPARE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS 018C ...
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TABLE 4-9: I2C1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C1RCV 0200 — — — I2C1TRN 0202 — — — I2C1BRG 0204 — — — I2C1CON 0206 I2CEN — I2CSIDL SCLREL I2C1STAT 0208 ...
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TABLE 4-11: UART1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — ...
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TABLE 4-15: ADC1 REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0300 ADC1BUF0 AD1CON1 0320 ADON — ADSIDL ADDMABM AD1CON2 0322 VCFG<2:0> — AD1CON3 0324 ADRC — — AD1CHS123 0326 — — — — AD1CHS0 ...
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TABLE 4-17: DMA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA0CON 0380 CHEN SIZE DIR HALF DMA0REQ 0382 FORCE — — — DMA0STA 0384 DMA0STB 0386 DMA0PAD 0388 DMA0CNT 038A — — — — ...
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TABLE 4-17: DMA REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA5CNT 03C6 — — — — DMA6CON 03C8 CHEN SIZE DIR HALF DMA6REQ 03CA FORCE — — — DMA6STA 03CC DMA6STB 03CE DMA6PAD ...
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TABLE 4-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = FOR dsPIC33FJXXXGP506A/51A0/706A/708A/710A DEVICES ONLY File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1CTRL1 0400 — — CSIDL ABAT C1CTRL2 0402 — — — C1VEC 0404 — ...
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TABLE 4-20: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 FOR dsPIC33FJXXXGP506A/510A/706A/708A/710A DEVICES ONLY File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0400- 041E C1BUFPNT1 0420 F3BP<3:0> C1BUFPNT2 0422 F7BP<3:0> C1BUFPNT3 0424 F11BP<3:0> C1BUFPNT4 0426 F15BP<3:0> C1RXM0SID 0430 ...
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TABLE 4-20: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 FOR dsPIC33FJXXXGP506A/510A/706A/708A/710A DEVICES ONLY File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1RXF11SID 046C SID<10:3> C1RXF11EID 046E EID<15:8> C1RXF12SID 0470 SID<10:3> C1RXF12EID 0472 EID<15:8> C1RXF13SID 0474 SID<10:3> C1RXF13EID ...
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TABLE 4-21: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = FOR dsPIC33FJXXXGP706A/708A/710A DEVICES ONLY File Name Addr Bit 15 Bit 14 Bit 13 C2CTRL1 0500 — — CSIDL C2CTRL2 0502 — — — C2VEC 0504 — — — C2FCTRL ...
Page 66
TABLE 4-23: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 FOR dsPIC33FJXXXGP706A/708A/710A DEVICES ONLY File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0500 - 051E C2BUFPNT1 0520 F3BP<3:0> C2BUFPNT2 0522 F7BP<3:0> C2BUFPNT3 0524 F11BP<3:0> C2BUFPNT4 0526 F15BP<3:0> C2RXM0SID ...
Page 67
TABLE 4-23: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 FOR dsPIC33FJXXXGP706A/708A/710A DEVICES ONLY (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C2RXF10EID 056A EID<15:8> C2RXF11SID 056C SID<10:3> C2RXF11EID 056E EID<15:8> C2RXF12SID 0570 SID<10:3> C2RXF12EID 0572 EID<15:8> ...
Page 68
TABLE 4-24: DCI REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name DCICON1 0280 DCIEN — DCISIDL — DCICON2 0282 — — — — DCICON3 0284 — — — — DCISTAT 0286 — — — — ...
Page 69
TABLE 4-27: PORTC REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISC 02CC TRISC15 TRISC14 TRISC13 TRISC12 PORTC 02CE RC15 RC14 RC13 RC12 LATC 02D0 LATC15 LATC14 LATC13 LATC12 Legend unknown value ...
Page 70
TABLE 4-31: PORTG REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISG 02E4 TRISG15 TRISG14 TRISG13 TRISG12 PORTG 02E6 RG15 RG14 RG13 RG12 LATG 02E8 LATG15 LATG14 LATG13 LATG12 ODCG 06E4 ODCG15 ODCG14 ODCG13 ...
Page 71
... Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2011 Microchip Technology Inc. 4.2.8 DATA RAM PROTECTION FEATURE The dsPIC33F product family supports Data RAM protection features which enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security ...
Page 72
... Modulo Addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into program space) and Y data spaces. Modulo Addressing © 2011 Microchip Technology Inc. ...
Page 73
... Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2011 Microchip Technology Inc. The length of a circular buffer is not directly specified determined by corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes) ...
Page 74
... If Bit-Reversed Addressing has already been enabled by setting the BREN bit (XBREV<15>), a write to the using XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. N bytes, should not be enabled disabled. However, Modulo © 2011 Microchip Technology Inc. ...
Page 75
... TABLE 4-36: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address © 2011 Microchip Technology Inc. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer Bit-Reversed Address Decimal ...
Page 76
... TBLPAG<7:0> 0xxx xxxx xxxx xxxx xxxx xxxx TBLPAG<7:0> 1xxx xxxx xxxx xxxx xxxx xxxx PSVPAG<7:0> xxxx xxxx © 2011 Microchip Technology Inc. show how the program EA is <14:1> <0> 0 xxxx xxx0 Data EA<15:0> Data EA<15:0> (1) Data EA<14:0> xxx xxxx xxxx xxxx ...
Page 77
... Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. © 2011 Microchip Technology Inc. Program Counter 0 23 bits ...
Page 78
... TBLRDL.B (Wn<0> TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in 0x800000 the user memory area. Section 5.0 “Flash © 2011 Microchip Technology Inc. ...
Page 79
... PAG is mapped into the upper half of the data memory space... © 2011 Microchip Technology Inc. 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...
Page 80
... NOTES: DS70593C-page 80 © 2011 Microchip Technology Inc. ...
Page 81
... Table Instruction User/Configuration Space Select © 2011 Microchip Technology Inc. Master Clear (MCLR). This allows customers to manu- facture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed ...
Page 82
... MINIMUM ROW WRITE TIME 11064 Cycles = × × 0.05 1 0.00375 + – Equation 5-3. MAXIMUM ROW WRITE TIME 11064 Cycles = × × 0.05 1 0.00375 – – (Register 5-1) controls which 5- write-only register that is Section 5.3 for further details. © 2011 Microchip Technology Inc. ...
Page 83
... Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2011 Microchip Technology Inc. (1) U-0 U-0 — — (1) U-0 ...
Page 84
... NVMKEY<7:0>: Key Register (Write Only) bits DS70593C-page 84 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown ...
Page 85
... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2011 Microchip Technology Inc. 4. Write the first 64 instructions from data RAM into the program memory buffers (see 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit ...
Page 86
... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted © 2011 Microchip Technology Inc. ...
Page 87
... Regulator V DD Trap Conflict Illegal Opcode Uninitialized W Register © 2011 Microchip Technology Inc. A simplified block diagram of the Reset module is shown in Figure Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. ...
Page 88
... DS70593C-page 88 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (3) (2) U-0 R/W-0 (3) — — VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 89
... All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. 3: For dsPIC33FJ256GPX06A/X08A/X10A devices, this bit is unimplemented and reads back programmed value. © 2011 Microchip Technology Inc. (1) (CONTINUED) DS70593C-page 89 ...
Page 90
... FSCM begins to monitor the system clock source after the SYSRST signal is released. Clearing Event POR, BOR POR, BOR POR POR, BOR PWRSAV instruction, POR, BOR POR, BOR POR, BOR — — Table 6-3. The system Reset signal, © 2011 Microchip Technology Inc. ...
Page 91
... SYSRST is released valid clock source is not available at this time, the device automatically switches to the FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine. © 2011 Microchip Technology Inc. System Clock SYSRST Delay Delay T ...
Page 92
... NOTES: DS70593C-page 92 © 2011 Microchip Technology Inc. ...
Page 93
... These are summarized in Table 7-2. © 2011 Microchip Technology Inc. 7.1.1 ALTERNATE VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in AIVT ...
Page 94
... Table 7-1 for the list of implemented interrupt vectors. DS70593C-page 94 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 (1) (1) © 2011 Microchip Technology Inc. ...
Page 95
... Microchip Technology Inc. AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Capture 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C DMA0 – DMA Channel 0 0x00011E IC2 – ...
Page 96
... AIVT Address 0x000004 0x000104 0x000006 0x000106 0x000008 0x000108 0x00000A 0x00010A 0x00000C 0x00010C 0x00000E 0x00010E 0x000010 0x000110 0x000012 0x000112 Interrupt Source Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error DMA Error Trap Reserved Reserved © 2011 Microchip Technology Inc. ...
Page 97
... The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2011 Microchip Technology Inc. The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels ...
Page 98
... R/C-0 (2) ACCSAT IPL3 -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) Register 3-2. R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 R-0 R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 R/W-0 PSV RND IF bit 0 ‘1’ = Bit is set © 2011 Microchip Technology Inc. ...
Page 99
... DMA controller error trap has occurred 0 = DMA controller error trap has not occurred bit 4 MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE ...
Page 100
... Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70593C-page 100 © 2011 Microchip Technology Inc. ...
Page 101
... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...
Page 102
... Interrupt request has not occurred DS70593C-page 102 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF R/W-0 R/W-0 R/W-0 DMA01IF T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 103
... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011 Microchip Technology Inc. DS70593C-page 103 ...
Page 104
... Interrupt request has not occurred DS70593C-page 104 R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF R/W-0 R/W-0 U-0 INT1IF CNIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC3IF DMA21IF bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 105
... MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011 Microchip Technology Inc. DS70593C-page 105 ...
Page 106
... Interrupt request has not occurred DS70593C-page 106 R/W-0 R/W-0 R/W-0 OC8IF OC7IF OC6IF R/W-0 R/W-0 R/W-0 DMA3IF C1IF C1RXIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC5IF IC6IF bit 8 R/W-0 R/W-0 SPI2IF SPI2EIF bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 107
... SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011 Microchip Technology Inc. DS70593C-page 107 ...
Page 108
... Interrupt request has not occurred DS70593C-page 108 R/W-0 R/W-0 U-0 DCIIF DCIEIF — R/W-0 R/W-0 R/W-0 T9IF T8IF MI2C2IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-0 — C2IF bit 8 R/W-0 R/W-0 SI2C2IF T7IF bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 109
... Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1EIF: UART1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...
Page 110
... Interrupt request not enabled DS70593C-page 110 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE R/W-0 R/W-0 R/W-0 DMA0IE T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1EIE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 111
... Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. DS70593C-page 111 ...
Page 112
... Interrupt request not enabled DS70593C-page 112 R/W-0 R/W-0 R/W-0 T5IE T4IE OC4IE R/W-0 R/W-0 U-0 INT1IE CNIE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC3IE DMA2IE bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 113
... Unimplemented: Read as ‘0’ bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. DS70593C-page 113 ...
Page 114
... Interrupt request not enabled DS70593C-page 114 R/W-0 R/W-0 R/W-0 OC8IE OC7IE OC6IE R/W-0 R/W-0 R/W-0 DMA3IE C1IE C1RXIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC5IE IC6IE bit 8 R/W-0 R/W-0 SPI2IE SPI2EIE bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 115
... Interrupt request enabled 0 = Interrupt request not enabled bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. DS70593C-page 115 ...
Page 116
... Interrupt request not enabled DS70593C-page 116 R/W-0 R/W-0 U-0 DCIIE DCIEIE — R/W-0 R/W-0 R/W-0 T9IE T8IE MI2C2IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-0 — C2IE bit 8 R/W-0 R/W-0 SI2C2IE T7IE bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 117
... U2EIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 ...
Page 118
... Interrupt is priority 1 000 = Interrupt source is disabled DS70593C-page 118 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 119
... Unimplemented: Read as ‘0’ bit 2-0 DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...
Page 120
... Interrupt is priority 1 000 = Interrupt source is disabled DS70593C-page 120 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 121
... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — ...
Page 122
... Interrupt is priority 1 000 = Interrupt source is disabled DS70593C-page 122 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 123
... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...
Page 124
... Interrupt is priority 1 000 = Interrupt source is disabled DS70593C-page 124 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC4IP<2:0> bit 8 R/W-0 R/W-0 DMA2IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 125
... Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...
Page 126
... Interrupt is priority 1 000 = Interrupt source is disabled DS70593C-page 126 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 C1RXIP<2:0> bit 8 R/W-0 R/W-0 SPI2EIP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 127
... Unimplemented: Read as ‘0’ bit 2-0 DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...
Page 128
... Interrupt is priority 1 000 = Interrupt source is disabled DS70593C-page 128 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC6IP<2:0> bit 8 R/W-0 R/W-0 IC6IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 129
... Unimplemented: Read as ‘0’ bit 2-0 OC8IP<2:0>: Output Compare Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — ...
Page 130
... Interrupt is priority 1 000 = Interrupt source is disabled DS70593C-page 130 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 MI2C2IP<2:0> bit 8 R/W-0 R/W-0 T7IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 131
... Unimplemented: Read as ‘0’ bit 2-0 T9IP<2:0>: Timer9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...
Page 132
... Interrupt source is disabled DS70593C-page 132 R/W-0 U-0 U-0 — — U-0 U-0 R/W-1 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 C2IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 133
... Unimplemented: Read as ‘0’ bit 2-0 DCIIP<2:0>: DCI Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 — ...
Page 134
... Unimplemented: Read as ‘0’ DS70593C-page 134 U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U2EIP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 135
... Unimplemented: Read as ‘0’ bit 2-0 DMA6IP<2:0>: DMA Channel 6 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...
Page 136
... Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70593C-page 136 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 137
... If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2011 Microchip Technology Inc. 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...
Page 138
... NOTES: DS70593C-page 138 © 2011 Microchip Technology Inc. ...
Page 139
... CPU. To exploit the DMA capability, the corresponding user buffers or variables must be located in DMA RAM. The dsPIC33FJXXXGPX06A/X08A/X10A peripherals that can utilize DMA are listed in Table 8-1 their associated Interrupt Request (IRQ) numbers. © 2011 Microchip Technology Inc. TABLE 8-1: Peripheral INT0 Input Capture 1 Input Capture 2 Output Compare 1 ...
Page 140
... An additional pair of status registers, DMACS0 and DMACS1, are common to all DMAC channels. DS70593C-page 140 Peripheral Indirect Address DMA Controller DMA Channels DMA DS Bus DMA Ready Peripheral 3 CPU DMA CPU DMA CPU DMA DMA DMA Ready Ready Peripheral 2 Peripheral 1 © 2011 Microchip Technology Inc. ...
Page 141
... MODE<1:0>: DMA Channel Operating Mode Select bits 11 = One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer Continuous, Ping-Pong modes enabled 01 = One-Shot, Ping-Pong modes disabled 00 = Continuous, Ping-Pong modes disabled © 2011 Microchip Technology Inc. R/W-0 R/W-0 U-0 HALF NULLW — ...
Page 142
... U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) (2) (2) IRQSEL4 IRQSEL3 IRQSEL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) U-0 U-0 — — — bit 8 R/W-0 R/W-0 (2) (2) (2) IRQSEL1 IRQSEL0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 143
... R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 STB<15:0>: Secondary DMA RAM Start Address bits (source or destination) © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 STA<15:8> R/W-0 R/W-0 R/W-0 STA<7:0> Unimplemented bit, read as ‘0’ ...
Page 144
... U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (2) CNT<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 (2) CNT<9:8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 145
... XWCOL5: Channel 5 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 4 XWCOL4: Channel 4 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected © 2011 Microchip Technology Inc. R/C-0 R/C-0 R/C-0 PWCOL4 PWCOL3 PWCOL2 R/C-0 ...
Page 146
... Write collision detected write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected DS70593C-page 146 © 2011 Microchip Technology Inc. ...
Page 147
... PPST1: Channel 1 Ping-Pong Mode Status Flag bit 1 = DMA1STB register selected 0 = DMA1STA register selected bit 0 PPST0: Channel 0 Ping-Pong Mode Status Flag bit 1 = DMA0STB register selected 0 = DMA0STA register selected © 2011 Microchip Technology Inc. U-0 R-1 R-1 — LSTCH<3:0> R-0 R-0 R-0 ...
Page 148
... DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits DS70593C-page 148 R-0 R-0 R-0 DSADR<15:8> R-0 R-0 R-0 DSADR<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 149
... F P Throughout this document F P different when Doze mode is used in any ratio other than 1:1, which is the default. © 2011 Microchip Technology Inc. The dsPIC33FJXXXGPX06A/X08A/X10A oscillator system provides: • Various external and internal oscillator options as the clock sources • An on-chip PLL to scale the internal operating ...
Page 150
... MIPS. For a primary oscillator or FRC oscillator, output ‘F the PLL output ‘F ’ is given by: OSC EQUATION 9-2: F OSC F F OSC = IN © 2011 Microchip Technology Inc. Configuration bits, Table 9-1. is divided OSC ) and the defines the P CY ...
Page 151
... Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL (FRCPLL) Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2011 Microchip Technology Inc. EQUATION 9- ------------- CY = 0.8-8.0 MHz 100-200 MHz ...
Page 152
... This is register is reset only on a Power-on Reset (POR). DS70593C-page 152 (1,3) R-0 U-0 R/W-y — NOSC<2:0> U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) © 2011 Microchip Technology Inc. R/W-y R/W-y (2) bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Clear only bit x = Bit is unknown ...
Page 153
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: This is register is reset only on a Power-on Reset (POR). © 2011 Microchip Technology Inc. (1,3) (CONTINUED) DS70593C-page 153 ...
Page 154
... This is register is reset only on a Power-on Reset (POR). DS70593C-page 154 (2) R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 155
... Note 1: This is register is reset only on a Power-on Reset (POR). © 2011 Microchip Technology Inc. (1) U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ...
Page 156
... This is register is reset only on a Power-on Reset (POR). DS70593C-page 156 (2) U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (1) TUN<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 157
... NOSC control bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. © 2011 Microchip Technology Inc valid clock switch has been initiated, the sta- tus bits, (OSCCON< ...
Page 158
... NOTES: DS70593C-page 158 © 2011 Microchip Technology Inc. ...
Page 159
... EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2011 Microchip Technology Inc. 10.2 Instruction-Based Power-Saving Modes dsPIC33FJXXXGPX06A/X08A/X10A devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction ...
Page 160
... If a PMD bit is set, the corresponding module is disabled after a delay of 1 instruction cycle. Similarly PMD bit is cleared, the corresponding module is enabled after a delay of 1 instruction cycle (assuming the module control registers are already configured to enable module operation). consumption in event-driven ® DSC © 2011 Microchip Technology Inc. ...
Page 161
... SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled Note 1: PCFGx bits have no effect if ADC module is disabled by setting this bit. In this case all port pins multiplexed with ANx will be in Digital mode. © 2011 Microchip Technology Inc. R/W-0 R/W-0 U-0 T2MD T1MD — ...
Page 162
... AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled Note 1: PCFGx bits have no effect if ADC module is disabled by setting this bit. In this case all port pins multiplexed with ANx will be in Digital mode. DS70593C-page 162 (1) © 2011 Microchip Technology Inc. ...
Page 163
... OC6MD: Output Compare 6 Module Disable bit 1 = Output Compare 6 module is disabled 0 = Output Compare 6 module is enabled bit 4 OC5MD: Output Compare 5 Module Disable bit 1 = Output Compare 5 module is disabled 0 = Output Compare 5 module is enabled © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 IC5MD IC4MD IC3MD R/W-0 ...
Page 164
... Output Compare 3 module is enabled bit 1 OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled DS70593C-page 164 © 2011 Microchip Technology Inc. ...
Page 165
... AD2MD: AD2 Module Disable bit 1 = AD2 module is disabled 0 = AD2 module is enabled Note 1: PCFGx bits have no effect if ADC module is disabled by setting this bit. In this case all port pins multi- plexed with ANx will be in Digital mode. © 2011 Microchip Technology Inc. R/W-0 U-0 U-0 T6MD — ...
Page 166
... NOTES: DS70593C-page 166 © 2011 Microchip Technology Inc. ...
Page 167
... CK Data Latch Read LAT Read Port © 2011 Microchip Technology Inc. has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through”, in which a port’s digital output can drive the input of a peripheral that shares the same pin. ...
Page 168
... CN pins. Setting in either any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. capable of detecting input © 2011 Microchip Technology Inc. ...
Page 169
... SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2011 Microchip Technology Inc. Timer1 also supports these features: • Timer gate operation • Selectable prescaler settings • Timer operation during CPU Idle and Sleep modes comprehensive • Interrupt on 16-bit Period register match or falling ...
Page 170
... Unimplemented: Read as ‘0’ DS70593C-page 170 U-0 U-0 — — R/W-0 U-0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TCS — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 171
... For 32-bit timer/counter operation, Timer2, Timer4, Timer6 or Timer8 is the least significant word; Timer3, Timer5, Timer7 or Timer9 is the most significant word of the 32-bit timers. © 2011 Microchip Technology Inc. Note: For 32-bit operation, T3CON, T5CON, T7CON and T9CON control bits are ignored. Only T2CON, T4CON, T6CON and T8CON control bits are used for setup and control ...
Page 172
... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70593C-page 172 (1) 1x Gate Sync PR2 PR3 Comparator LSb TMR3 TMR2 TMR3HLD 16 TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2011 Microchip Technology Inc. ...
Page 173
... FIGURE 13-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2011 Microchip Technology Inc. 1x Gate Sync TMR2 Sync Comparator PR2 TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 TCS TGATE DS70593C-page 173 ...
Page 174
... R/W-0 R/W-0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ) “Pin Diagrams” section for the available pins. U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 (1) — TCS — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 175
... When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 3: The TyCK pin is not available on all timers. Refer to the © 2011 Microchip Technology Inc. U-0 U-0 (2) — — ...
Page 176
... NOTES: DS70593C-page 176 © 2011 Microchip Technology Inc. ...
Page 177
... ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2011 Microchip Technology Inc. • Capture timer value on every edge (rising and fall- ing) • Prescaler Capture Event modes: - Capture timer value on every 4th rising ...
Page 178
... Input capture module turned off DS70593C-page 178 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 179
... TMR3 TMR2 © 2011 Microchip Technology Inc. The output compare module can select either Timer2 or Timer3 for its time base. The module compares the value of the timer with the value of one or two Compare registers depending on the operating mode selected. The state of the output pin changes when the timer value matches the Compare register value ...
Page 180
... OCx rising and falling edge OCx falling edge 0 OCx falling edge 0 ‘0’, if OCxR is zero No interrupt ‘1’, if OCxR is non-zero ‘0’, if OCxR is zero OCFA falling edge for OC1 to OC4 ‘1’, if OCxR is non-zero Timer is Reset on Period Match © 2011 Microchip Technology Inc. — ...
Page 181
... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2011 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 182
... NOTES: DS70593C-page 182 © 2011 Microchip Technology Inc. ...
Page 183
... SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF © 2011 Microchip Technology Inc. The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, Analog-to-Digital Converters (ADC), etc ...
Page 184
... Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. DS70593C-page 184 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R-0 R-0 SPITBF SPIRBF bit Bit is unknown ...
Page 185
... The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1 not set both Primary and Secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1. © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 DISSCK DISSDO ...
Page 186
... The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1 not set both Primary and Secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1. DS70593C-page 186 (2) (2) © 2011 Microchip Technology Inc. ...
Page 187
... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: Read as ‘0’ This bit must not be set to ‘1’ by the user application. © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — ...
Page 188
... NOTES: DS70593C-page 188 © 2011 Microchip Technology Inc. ...
Page 189
... I C supports multi-master operation; detects bus collision and will arbitrate accordingly © 2011 Microchip Technology Inc. 17.1 Operating Modes The hardware fully implements all the master and slave 2 functions of the I specifications, as well as 7 and 10-bit addressing ...
Page 190
... Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2011 Microchip Technology Inc. ...
Page 191
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2011 Microchip Technology Inc. R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...
Page 192
... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence 0 = Start condition not in progress DS70593C-page 192 2 C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte 2 C master master master) © 2011 Microchip Technology Inc. ...
Page 193
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2011 Microchip Technology Inc. U-0 U-0 R/C-0 HS — — ...
Page 194
... Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70593C-page 194 2 C slave device address byte. © 2011 Microchip Technology Inc. ...
Page 195
... AMSKx: Mask for Address Bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2011 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 196
... NOTES: DS70593C-page 196 © 2011 Microchip Technology Inc. ...
Page 197
... UART1 or UART2 transmission or reception DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word (i.e., UTXISEL<1:0> and URXISEL<1:0> = 00). © 2011 Microchip Technology Inc. The primary features of the UART module are: • Full-Duplex 9-bit Data Transmission through the UxTX and UxRX pins • ...
Page 198
... DS70593C-page 198 MODE REGISTER x R/W-0 R/W-0 U-0 (2) IREN RTSMD — R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) R/W-0 R/W-0 UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 199
... Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2011 Microchip Technology Inc. MODE REGISTER (CONTINUED) x DS70593C-page 199 ...
Page 200
... U-0 R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR C = Clear only bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R-0 R-1 (1) UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Bit is unknown © 2011 Microchip Technology Inc. ...