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ATMEGA16L-8AU
ATMEGA16L-8AU | |
|---|---|
| Manufacturer Part Number | ATMEGA16L-8AU |
| Description | IC AVR MCU 16K 8MHZ 3V 44TQFP |
| Manufacturer | Atmel |
| Series | AVR® ATmega |
| ATMEGA16L-8AU datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
×
Shipping terms
- Standard delivery time differs from 5-8 business days if the supplier is a local one to 12-14 days if the suplier is from overseas. If delivery time differs it's always mentioned in our quotation.
- We ship worldwide using main international couriers like FedEx, DHL, UPS, TNT, EMS. We can also use client's freight account. Other shipping methods can be discussed. We do best to meet your needs!
Payment terms
- For new client payment term is payment in advance. At this moment we accept 3 payment methods: wire transfer, PayPal and Western Union. Credit card payment is under constrution and will be introduced soon. Escrow service is acceptable. Net terms for regular customers is not a problem. Working with us is totally safe for you.
- If you still have any questions - please contact us
Specifications of ATMEGA16L-8AU | |||
|---|---|---|---|
| Core Processor | AVR | Core Size | 8-Bit |
| Speed | 8MHz | Connectivity | I²C, SPI, UART/USART |
| Peripherals | Brown-out Detect/Reset, POR, PWM, WDT | Number Of I /o | 32 |
| Program Memory Size | 16KB (8K x 16) | Program Memory Type | FLASH |
| Eeprom Size | 512 x 8 | Ram Size | 1K x 8 |
| Voltage - Supply (vcc/vdd) | 2.7 V ~ 5.5 V | Data Converters | A/D 8x10b |
| Oscillator Type | Internal | Operating Temperature | -40°C ~ 85°C |
| Package / Case | 44-TQFP, 44-VQFP | Processor Series | ATMEGA16x |
| Core | AVR8 | Data Bus Width | 8 bit |
| Data Ram Size | 1 KB | Interface Type | JTAG/SPI/UART |
| Maximum Clock Frequency | 8 MHz | Number Of Programmable I/os | 32 |
| Number Of Timers | 3 | Operating Supply Voltage | 2.7 V to 5.5 V |
| Maximum Operating Temperature | + 85 C | Mounting Style | SMD/SMT |
| 3rd Party Development Tools | EWAVR, EWAVR-BL | Minimum Operating Temperature | - 40 C |
| On-chip Adc | 8-ch x 10-bit | For Use With | ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
PrevNext
Mnemonics
Operands
Description
BRIE
k
Branch if Interrupt Enabled
BRID
k
Branch if Interrupt Disabled
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move Between Registers
MOVW
Rd, Rr
Copy Register Word
LDI
Rd, K
Load Immediate
LD
Rd, X
Load Indirect
LD
Rd, X+
Load Indirect and Post-Inc.
LD
Rd, - X
Load Indirect and Pre-Dec.
LD
Rd, Y
Load Indirect
LD
Rd, Y+
Load Indirect and Post-Inc.
LD
Rd, - Y
Load Indirect and Pre-Dec.
LDD
Rd,Y+q
Load Indirect with Displacement
LD
Rd, Z
Load Indirect
LD
Rd, Z+
Load Indirect and Post-Inc.
LD
Rd, -Z
Load Indirect and Pre-Dec.
LDD
Rd, Z+q
Load Indirect with Displacement
LDS
Rd, k
Load Direct from SRAM
ST
X, Rr
Store Indirect
ST
X+, Rr
Store Indirect and Post-Inc.
ST
- X, Rr
Store Indirect and Pre-Dec.
ST
Y, Rr
Store Indirect
ST
Y+, Rr
Store Indirect and Post-Inc.
ST
- Y, Rr
Store Indirect and Pre-Dec.
STD
Y+q,Rr
Store Indirect with Displacement
ST
Z, Rr
Store Indirect
ST
Z+, Rr
Store Indirect and Post-Inc.
ST
-Z, Rr
Store Indirect and Pre-Dec.
STD
Z+q,Rr
Store Indirect with Displacement
STS
k, Rr
Store Direct to SRAM
LPM
Load Program Memory
LPM
Rd, Z
Load Program Memory
LPM
Rd, Z+
Load Program Memory and Post-Inc
SPM
Store Program Memory
IN
Rd, P
In Port
OUT
P, Rr
Out Port
PUSH
Rr
Push Register on Stack
POP
Rd
Pop Register from Stack
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
CBI
P,b
Clear Bit in I/O Register
LSL
Rd
Logical Shift Left
LSR
Rd
Logical Shift Right
ROL
Rd
Rotate Left Through Carry
ROR
Rd
Rotate Right Through Carry
ASR
Rd
Arithmetic Shift Right
SWAP
Rd
Swap Nibbles
BSET
s
Flag Set
BCLR
s
Flag Clear
BST
Rr, b
Bit Store from Register to T
BLD
Rd, b
Bit load from T to Register
SEC
Set Carry
CLC
Clear Carry
SEN
Set Negative Flag
CLN
Clear Negative Flag
SEZ
Set Zero Flag
CLZ
Clear Zero Flag
SEI
Global Interrupt Enable
CLI
Global Interrupt Disable
SES
Set Signed Test Flag
CLS
Clear Signed Test Flag
SEV
Set Twos Complement Overflow.
CLV
Clear Twos Complement Overflow
SET
Set T in SREG
CLT
Clear T in SREG
SEH
Set Half Carry Flag in SREG
ATmega16(L)
10
Flags
Operation
if ( I = 1) then PC ← PC + k + 1
None
if ( I = 0) then PC ← PC + k + 1
None
Rd ← Rr
None
Rd+1:Rd ← Rr+1:Rr
None
Rd ← K
None
Rd ← (X)
None
Rd ← (X), X ← X + 1
None
X ← X - 1, Rd ← (X)
None
Rd ← (Y)
None
Rd ← (Y), Y ← Y + 1
None
Y ← Y - 1, Rd ← (Y)
None
Rd ← (Y + q)
None
Rd ← (Z)
None
Rd ← (Z), Z ← Z+1
None
Z ← Z - 1, Rd ← (Z)
None
Rd ← (Z + q)
None
Rd ← (k)
None
(X) ← Rr
None
(X) ← Rr, X ← X + 1
None
X ← X - 1, (X) ← Rr
None
(Y) ← Rr
None
(Y) ← Rr, Y ← Y + 1
None
Y ← Y - 1, (Y) ← Rr
None
(Y + q) ← Rr
None
(Z) ← Rr
None
(Z) ← Rr, Z ← Z + 1
None
Z ← Z - 1, (Z) ← Rr
None
(Z + q) ← Rr
None
(k) ← Rr
None
R0 ← (Z)
None
Rd ← (Z)
None
Rd ← (Z), Z ← Z+1
None
(Z) ← R1:R0
None
Rd ← P
None
P ← Rr
None
STACK ← Rr
None
Rd ← STACK
None
I/O(P,b) ← 1
None
I/O(P,b) ← 0
None
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
SREG(s) ← 1
SREG(s)
SREG(s) ← 0
SREG(s)
T ← Rr(b)
T
Rd(b) ← T
None
C ← 1
C
C ← 0
C
N ← 1
N
N ← 0
N
Z ← 1
Z
Z ← 0
Z
I ← 1
I
I ← 0
I
S ← 1
S
S ← 0
S
V ← 1
V
V ← 0
V
T ← 1
T
T ← 0
T
H ← 1
H
#Clocks
1 / 2
1 / 2
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
-
1
1
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2466TS–AVR–07/10
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