DSPIC30F4013-30I/PT Microchip Technology, DSPIC30F4013-30I/PT Datasheet - Page 221

• Manufacturer Part Number: DSPIC30F4013-30I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-30I/PT

• Program Memory Type: FLASH
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 1024 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401330IPT

I
I
I
I
I
Idle Current (I
In-Circuit Serial Programming (ICSP) ......................... 43, 141
Input Capture Module ......................................................... 81
Input Capture Operation During Sleep and Idle Modes ...... 82
Input Capture Timing Requirements ................................. 190
Input Change Notification Module ....................................... 56
Instruction Addressing Modes............................................. 37
Instruction Set
Internal Clock Timing Examples ....................................... 183
Internet Address................................................................ 225
Interrupt Controller
Interrupt Priority .................................................................. 60
Interrupt Sequence ............................................................. 63
Interrupts ............................................................................. 59
L
Load Conditions ................................................................ 181
Low-Voltage Detect (LVD) ................................................ 155
 2010 Microchip Technology Inc.
2
2
2
2
2
C 7-Bit Slave Mode Operation.......................................... 93
C Master Mode Operation ................................................ 95
C Master Mode Support ................................................... 95
C Module .......................................................................... 91
S Mode Operation .......................................................... 129
Transmission............................................................... 93
Reception.................................................................... 93
Transmission............................................................... 93
Baud Rate Generator.................................................. 96
Clock Arbitration.......................................................... 96
Multi-Master Communication,
Reception.................................................................... 96
Transmission............................................................... 95
Addresses ................................................................... 93
Bus Data Timing Requirements
General Call Address Support .................................... 95
Interrupts..................................................................... 95
IPMI Support ............................................................... 95
Operating Function Description .................................. 91
Operation During CPU Sleep and Idle Modes ............ 96
Pin Configuration ........................................................ 91
Programmer’s Model................................................... 91
Register Map............................................................... 97
Registers..................................................................... 91
Slope Control .............................................................. 95
Software Controlled Clock Stretching (STREN = 1).... 94
Various Modes ............................................................ 91
Data Justification....................................................... 129
Frame and Data Word Length Selection................... 129
Interrupts..................................................................... 82
Register Map............................................................... 83
CPU Idle Mode............................................................ 82
CPU Sleep Mode ........................................................ 82
Register Map............................................................... 57
File Register Instructions ............................................ 37
Fundamental Modes Supported.................................. 37
MAC Instructions......................................................... 38
MCU Instructions ........................................................ 37
Move and Accumulator Instructions............................ 38
Other Instructions........................................................ 38
Overview ................................................................... 162
Summary................................................................... 159
Register Map............................................................... 66
Traps........................................................................... 62
Interrupt Stack Frame ................................................. 63
Bus Collision and Bus Arbitration ....................... 96
Master Mode ..................................................... 201
Slave Mode ....................................................... 204
IDLE
) ............................................................ 175
LVDL Characteristics ........................................................ 179
M
Memory Organization ......................................................... 25
Microchip Internet Web Site.............................................. 225
Modes of Operation
Modulo Addressing ............................................................. 38
MPLAB ASM30 Assembler, Linker, Librarian ................... 168
MPLAB Integrated Development Environment Software.. 167
MPLAB PM3 Device Programmer .................................... 170
MPLAB REAL ICE In-Circuit Emulator System ................ 169
MPLINK Object Linker/MPLIB Object Librarian ................ 168
N
NVM
O
Operating Current (I
Operating Frequency vs Voltage
Oscillator
Oscillator Selection ........................................................... 141
Oscillator Start-up Timer
Output Compare Interrupts ................................................. 88
Output Compare Module .................................................... 85
Output Compare Operation During CPU Idle Mode ........... 88
Output Compare Sleep Mode Operation ............................ 88
P
Packaging Information ...................................................... 211
Peripheral Module Disable (PMD) Registers .................... 157
Pinout Descriptions............................................................. 13
POR. See Power-on Reset.
Power Saving Modes
Power-Down Current (I
Power-Saving Modes........................................................ 155
dsPIC30F3014/4013
Core Register Map ..................................................... 33
Disable...................................................................... 113
Initialization............................................................... 113
Listen All Messages.................................................. 113
Listen Only................................................................ 113
Loopback .................................................................. 113
Normal Operation ..................................................... 113
Applicability................................................................. 40
Incrementing Buffer Operation Example .................... 39
Start and End Address ............................................... 39
W Address Register Selection.................................... 39
Register Map .............................................................. 47
dsPIC30FXXXX-20 (Extended) ................................ 172
Configurations .......................................................... 144
Control Registers...................................................... 147
Operating Modes (Table).......................................... 142
System Overview...................................................... 141
Timing Requirements ............................................... 187
Register Map dsPIC30F3014 ..................................... 89
Register Map dsPIC30F4013 ..................................... 89
Timing Requirements ............................................... 190
Marking..................................................................... 211
Sleep and Idle........................................................... 141
Idle............................................................................ 156
Fail-Safe Clock Monitor .................................... 146
Fast RC (FRC).................................................. 145
Initial Clock Source Selection ........................... 144
Low-Power RC (LPRC) .................................... 145
LP Oscillator Control......................................... 145
Phase Locked Loop (PLL) ................................ 145
Start-up Timer (OST)........................................ 144
DD
) .................................................... 174
PD
)................................................ 176
DS70138G-page 221