DSPIC30F4013-30I/PT Microchip Technology, DSPIC30F4013-30I/PT Datasheet - Page 96

• Manufacturer Part Number: DSPIC30F4013-30I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-30I/PT

• Program Memory Type: FLASH
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 1024 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401330IPT

dsPIC30F3014/4013
14.12.2
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (I2CCON<3>). The I
module must be Idle before the RCEN bit is set; other-
wise, the RCEN bit is disregarded. The Baud Rate
Generator begins counting and on each rollover, the
state of the SCL pin ACK and data are shifted into the
I2CRSR on the rising edge of each clock.
14.12.3
In I
located in the I2CBRG register. When the BRG is
loaded with this value, the BRG counts down to ‘0’ and
stops until another reload has taken place. If clock
arbitration is taking place, for instance, the BRG is
reloaded when the SCL pin is sampled high.
As per the I
400 kHz. However, the user can specify any baud rate
up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal.
EQUATION 14-1:
14.12.4
Clock arbitration occurs when the master deasserts the
SCL pin (SCL allowed to float high) during any receive,
transmit, or Restart/Stop condition. When the SCL pin
is allowed to float high, the Baud Rate Generator
(BRG) is suspended from counting until the SCL pin is
actually sampled high. When the SCL pin is sampled
high, the Baud Rate Generator is reloaded with the
contents of I2CBRG and begins counting. This ensures
that the SCL high time is always at least one BRG roll-
over count in the event that the clock is held low by an
external device.
14.12.5
Multi-master operation support is achieved by bus arbi-
tration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
master outputs a ‘1’ on SDA by letting SDA float high
while another master asserts a ‘0’. When the SCL pin
floats high, data should be stable. If the expected data
on SDA is a ‘1’ and the data sampled on the SDA
pin = 0, then a bus collision has taken place. The
master sets the MI2CIF pulse and resetS the master
portion of the I
DS70138G-page 96
2
C Master mode, the reload value for the BRG is
I2CBRG =
I
BAUD RATE GENERATOR
CLOCK ARBITRATION
MULTI-MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
2
2
C MASTER RECEPTION
C standard, FSCK may be 100 kHz or
2
C port to its Idle state.
(
F
F
SCK
SERIAL CLOCK RATE
CY
–
1,111,111
F
CY
)
– 1
2
C
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the TBF flag is
cleared, the SDA and SCL lines are deasserted and a
value can now be written to I2CTRN. When the user
services the I
Routine, if the I
user can resume communication by asserting a Start
condition.
If a Start, Restart, Stop or Acknowledge condition was
in progress when the bus collision occurred, the condi-
tion is aborted, the SDA and SCL lines are deasserted
and the respective control bits in the I2CCON register
are cleared to ‘0’. When the user services the bus
collision Interrupt Service Routine, and if the I
free, the user can resume communication by asserting
a Start condition.
The master continues to monitor the SDA and SCL
pins, and if a Stop condition occurs, the MI2CIF bit is
set.
A write to the I2CTRN starts the transmission of data at
the first data bit, regardless of where the transmitter left
off when bus collision occurred.
In a multi-master environment, the interrupt generation
on the detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I
bus can be taken when the P bit is set in the I2CSTAT
register, or the bus is Idle and the S and P bits are
cleared.
14.13 I
14.13.1
When the device enters Sleep mode, all clock sources
to the module are shut down and stay at logic ‘0’. If
Sleep occurs in the middle of a transmission and the
state machine is partially into a transmission as the
clocks stop, then the transmission is aborted. Similarly,
if Sleep occurs in the middle of a reception, then the
reception is aborted.
14.13.2
For the I
stops or continues on Idle. If I2CSIDL = 0, the module
continues operation on assertion of the Idle mode. If
I2CSIDL = 1, the module stops on Idle.
2
Sleep and Idle Modes
C, the I2CSIDL bit determines if the module
2
C Module Operation During CPU
I
SLEEP MODE
I
MODE
2
2
C OPERATION DURING CPU
C OPERATION DURING CPU IDLE
2
2
C bus is free (i.e., the P bit is set), the
C master event Interrupt Service
 2010 Microchip Technology Inc.
2
C bus is
2
C