DSPIC30F4013-20I/PT Microchip Technology, DSPIC30F4013-20I/PT Datasheet - Page 123

• Manufacturer Part Number: DSPIC30F4013-20I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 30
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401320IPT

18.3
18.3.1
The DCI module is enabled or disabled by setting/
clearing the DCIEN control bit in the DCICON1 SFR.
Clearing the DCIEN control bit has the effect of reset-
ting the module. In particular, all counters associated
with CSCK generation, Frame Sync, and the DCI buffer
control unit are reset.
The DCI clocks are shut down when the DCIEN bit is
cleared.
When enabled, the DCI controls the data direction for
the four I/O pins associated with the module. The port,
LAT and TRIS register values for these I/O pins are
overridden by the DCI module when the DCIEN bit is set.
It is also possible to override the CSCK pin separately
when the bit clock generator is enabled. This permits
the bit clock generator to operate without enabling the
rest of the DCI module.
18.3.2
The WS<3:0> word-size selection bits in the DCICON2
SFR determine the number of bits in each DCI data
word. Essentially, the WS<3:0> bits determine the
counting period for a 4-bit counter clocked from the
CSCK signal.
Any data length, up to 16 bits, may be selected. The
value loaded into the WS<3:0> bits is one less the
desired word length. For example, a 16-bit data word
size is selected when WS<3:0> = 1111.
18.3.3
The Frame Sync generator (COFSG) is a 4-bit counter
that sets the frame length in data words. The Frame
Sync generator is incremented each time the word-size
counter is reset (refer to
Selection
zation generator is set by writing the COFSG<3:0>
control bits in the DCICON2 SFR. The COFSG period
in clock cycles is determined by the following formula:
EQUATION 18-1:
 2010 Microchip Technology Inc.
Note:
Frame Length = Word Length • (FSG Value + 1)
DCI Module Operation
Bits”). The period for the Frame Synchroni-
MODULE ENABLE
WORD-SIZE SELECTION BITS
These WS<3:0> control bits are used only
in the Multichannel and I
bits have no effect in AC-Link mode since
the data slot sizes are fixed by the protocol.
FRAME SYNC GENERATOR
COFSG PERIOD
Section 18.3.2 “Word-Size
2
S modes. These
Frame lengths, up to 16 data words, may be selected.
The frame length in CSCK periods can vary up to a
maximum of 256 depending on the word size that is
selected.
18.3.4
The type of Frame Sync signal is selected using the
Frame
(COFSM<1:0>) in the DCICON1 SFR. The following
operating modes can be selected:
• Multichannel mode
• I
• AC-Link mode (16-bit)
• AC-Link mode (20-bit)
The operation of the COFSM control bits depends on
whether the DCI module generates the Frame Sync
signal as a master device, or receives the Frame Sync
signal as a slave device.
The master device in a DSP/Codec pair is the device
that generates the Frame Sync signal. The Frame Sync
signal initiates data transfers on the CSDI and CSDO
pins and usually has the same frequency as the data
sample rate (COFS).
The DCI module is a Frame Sync master if the COFSD
control bit is cleared and is a Frame Sync slave if the
COFSD control bit is set.
18.3.5
When the DCI module is operating as a Frame Sync
master device (COFSD = 0), the COFSM mode bits
determine the type of Frame Sync pulse that is
generated by the Frame Sync generator logic.
A new COFS signal is generated when the Frame Sync
generator resets to ‘0’.
In the Multichannel mode, the Frame Sync pulse is
driven high for the CSCK period to initiate a data trans-
fer. The number of CSCK cycles between successive
Frame Sync pulses depends on the word size and
Frame Sync generator control bits. A timing diagram for
the Frame Sync signal in Multichannel mode is shown
in
In the AC-Link mode of operation, the Frame Sync
signal has a fixed period and duty cycle. The AC-Link
Frame Sync signal is high for 16 CSCK cycles and is
low for 240 CSCK cycles. A timing diagram with the
timing details at the start of an AC-Link frame is shown
in
In the I
duty cycle is generated. The period of the I
Sync signal in CSCK cycles is determined by the word
Note:
Figure
Figure
2
dsPIC30F3014/4013
S mode
2
S mode, a Frame Sync signal having a 50%
18-2.
18-3.
Synchronization
The COFSG control bits have no effect in
AC-Link mode since the frame length is
set to 256 CSCK periods by the protocol.
FRAME SYNC MODE
CONTROL BITS
MASTER FRAME SYNC
OPERATION
mode
DS70138G-page 123
control
2
S Frame
bits