DSPIC30F4013-20I/PT Microchip Technology, DSPIC30F4013-20I/PT Datasheet - Page 137

• Manufacturer Part Number: DSPIC30F4013-20I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 30
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401320IPT

19.9
The module has two internal power modes.
When the ADON bit is ‘1’, the module is in Active mode;
it is fully powered and functional.
When ADON is ‘0’, the module is in Off mode. The
digital and analog portions of the circuit are disabled for
maximum current savings.
In order to return to the Active mode from Off mode, the
user must wait for the ADC circuitry to stabilize. The
time required to stabilize is specified in
“Electrical
19.10 A/D Operation During CPU Sleep
19.10.1
When the device enters Sleep mode, all clock sources
to the module are shut down and stay at logic ‘0’.
If Sleep occurs in the middle of a conversion, the
conversion is aborted. The converter does not continue
with a partially completed conversion on exit from
Sleep mode.
Register contents are not affected by the device
entering or leaving Sleep mode.
The A/D module can operate during Sleep mode if the
A/D clock source is set to RC (ADRC = 1). When the
RC clock source is selected, the A/D module waits one
instruction cycle before starting the conversion. This
allows the SLEEP instruction to be executed which
eliminates all digital switching noise from the conver-
sion. (When the conversion sequence is complete, the
DONE bit is set.)
FIGURE 19-5:
 2010 Microchip Technology Inc.
RAM Contents:
Read to Bus:
Module Power-Down Modes
and Idle Modes
Signed Fractional
Characteristics”.
A/D OPERATION DURING CPU
SLEEP MODE
Signed Integer
Fractional
Integer
A/D OUTPUT DATA FORMATS
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d11 d11 d11 d11 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
0
0
Section 23.0
0
0
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
If the A/D interrupt is enabled, the device wakes up
from Sleep. If the A/D interrupt is not enabled, the A/D
module is then turned off, although the ADON bit
remains set.
19.10.2
The ADSIDL bit determines if the module stops or
continues on Idle. If ADSIDL = 0, the module continues
operation on assertion of Idle mode. If ADSIDL = 1, the
module stops on Idle.
19.11 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off, and any
conversion and sampling sequence is aborted. The val-
ues that are in the ADCBUF registers are not modified.
The A/D Result register contains unknown data after a
Power-on Reset.
19.12 Output Formats
The A/D result is 12 bits wide. The data buffer RAM is
also 12 bits wide. The 12-bit data can be read in one
of four different formats. The FORM<1:0> bits select
the format. Each of the output formats translates to a
16-bit result on the data bus. Write data is always in
right-justified (integer) format.
dsPIC30F3014/4013
A/D OPERATION DURING CPU IDLE
MODE
0
0
DS70138G-page 137
0
0
0
0
0
0