DSPIC30F4013-20I/PT Microchip Technology, DSPIC30F4013-20I/PT Datasheet - Page 67

• Manufacturer Part Number: DSPIC30F4013-20I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 30
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401320IPT

9.0
This section describes the 16-bit general purpose
Timer1 module and associated operational modes.
Figure 9-1
16-bit Timer1 module.
The following sections provide a detailed description
including setup and control registers, along with
associated block diagrams for the operational modes of
the timers.
The Timer1 module is a 16-bit timer which can serve as
the time counter for the Real-Time Clock (RTC), or
operate as a free-running interval timer/counter. The
16-bit timer has the following modes:
• 16-bit Timer
• 16-bit Synchronous Counter
• 16-bit Asynchronous Counter
Further, the following operational characteristics are
supported:
• Timer gate operation
• Selectable prescaler settings
• Timer operation during CPU Idle and Sleep
• Interrupt on 16-bit Period register match or falling
FIGURE 9-1:
 2010 Microchip Technology Inc.
Note:
modes
edge of external gate signal
TIMER1 MODULE
SOSCO/
depicts the simplified block diagram of the
T1IF
Event Flag
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
SOSCI
T1CK
16-BIT TIMER1 MODULE BLOCK DIAGRAM
TGATE
0
1
Equal
Reset
LPOSCEN
Comparator x 16
TMR1
PR1
Q
Q
Gate
Sync
CK
T
CY
D
These operating modes are determined by setting the
appropriate bit(s) in the 16-bit SFR, T1CON.
presents a block diagram of the 16-bit timer module.
16-Bit Timer Mode: In the 16-Bit Timer mode, the
timer increments on every instruction cycle up to a
match value preloaded into the Period register, PR1,
then resets to ‘0’ and continues to count.
When the CPU goes into the Idle mode, the timer stops
incrementing unless the TSIDL (T1CON<13>) bit = 0.
If TSIDL = 1, the timer module logic resumes the incre-
menting sequence upon termination of the CPU Idle
mode.
16-Bit Synchronous Counter Mode: In the 16-Bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.
When the CPU goes into the Idle mode, the timer stops
incrementing unless the respective TSIDL bit = 0. If
TSIDL = 1, the timer module logic resumes the incre-
menting sequence upon termination of the CPU Idle
mode.
16-Bit Asynchronous Counter Mode: In the 16-Bit
Asynchronous Counter mode, the timer increments on
every rising edge of the applied external clock signal.
The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.
When the timer is configured for the Asynchronous
mode of operation and the CPU goes into the Idle
mode, the timer stops incrementing if TSIDL = 1.
TGATE
dsPIC30F3014/4013
1 x
0 1
0 0
TON
TSYNC
1
0
TCKPS<1:0>
1, 8, 64, 256
Prescaler
Sync
2
DS70138G-page 67
Figure 9-1