DSPIC30F4013-20I/PT Microchip Technology, DSPIC30F4013-20I/PT Datasheet - Page 68

• Manufacturer Part Number: DSPIC30F4013-20I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 30
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401320IPT

dsPIC30F3014/4013
9.1
The 16-bit timer can be placed in the Gated Time Accu-
mulation mode. This mode allows the internal T
increment the respective timer when the gate input sig-
nal (T1CK pin) is asserted high. Control bit, TGATE
(T1CON<6>), must be set to enable this mode. The
timer must be enabled (TON = 1) and the timer clock
source set to internal (TCS = 0).
When the CPU goes into the Idle mode, the timer stops
incrementing unless TSIDL = 0. If TSIDL = 1, the timer
resumes the incrementing sequence upon termination
of the CPU Idle mode.
9.2
The input clock (F
Timer has a prescale option of 1:1, 1:8, 1:64 and 1:256,
selected by control bits, TCKPS<1:0> (T1CON<5:4>).
The prescaler counter is cleared when any of the
following occurs:
• a write to the TMR1 register
• a write to the T1CON register
• device Reset, such as POR and BOR
However, if the timer is disabled (TON = 0), then the
timer prescaler cannot be reset since the prescaler
clock is halted.
TMR1 is not cleared when T1CON is written. It is
cleared by writing to the TMR1 register.
9.3
During CPU Sleep mode, the timer operates if:
• The timer module is enabled (TON = 1) and
• The timer clock source is selected as external
• The TSYNC bit (T1CON<2>) is asserted to a logic
When all three conditions are true, the timer continues
to count up to the Period register and is reset to
0x0000.
When a match between the timer and the Period
register occurs, an interrupt can be generated if the
respective timer interrupt enable bit is asserted.
9.4
The 16-bit timer has the ability to generate an interrupt-
on-period match. When the timer count matches the
Period register, the T1IF bit is asserted and an interrupt
is generated, if enabled. The T1IF bit must be cleared in
software. The Timer Interrupt Flag, T1IF, is located in the
IFS0 Control register in the interrupt controller.
When the Gated Time Accumulation mode is enabled,
an interrupt is also generated on the falling edge of the
gate signal (at the end of the accumulation cycle).
DS70138G-page 68
(TCS = 1) and
‘0’ which defines the external clock source as
asynchronous.
Timer Gate Operation
Timer Prescaler
Timer Operation During Sleep
Mode
Timer Interrupt
OSC
/4 or external clock) to the 16-bit
CY
to
Enabling an interrupt is accomplished via the respec-
tive timer interrupt enable bit, T1IE. The timer interrupt
enable bit is located in the IEC0 Control register in the
interrupt controller.
9.5
Timer1, when operating in Real-Time Clock (RTC)
mode, provides time of day and event time-stamping
capabilities. Key operational features of the RTC are:
• Operation from 32 kHz LP oscillator
• 8-bit prescaler
• Low power
• Real-Time Clock interrupts
These operating modes are determined by setting the
appropriate bit(s) in the T1CON Control register.
FIGURE 9-2:
9.5.1
When the TON = 1, TCS = 1 and TGATE = 0, the timer
increments on the rising edge of the 32 kHz LP oscilla-
tor output signal, up to the value specified in the Period
register and is then reset to ‘0’.
The TSYNC bit must be asserted to a logic ‘0’
(Asynchronous mode) for correct operation.
Enabling LPOSCEN (OSCCON<1>) disables the nor-
mal Timer and Counter modes and enable a timer
carry-out wake-up event.
When the CPU enters Sleep mode, the RTC continues
to operate, provided the 32 kHz external crystal oscilla-
tor is active and the control bits have not been
changed. The TSIDL bit should be cleared to ‘0’ in
order for RTC to continue operation in Idle mode.
9.5.2
When an interrupt event occurs, the respective interrupt
flag, T1IF, is asserted and an interrupt is generated, if
enabled. The T1IF bit must be cleared in software. The
respective Timer Interrupt Flag, T1IF, is located in the
IFS0 register in the interrupt controller.
Enabling an interrupt is accomplished via the respec-
tive timer interrupt enable bit, T1IE. The timer interrupt
enable bit is located in the IEC0 Control register in the
interrupt controller.
C1 = C2 = 18 pF; R = 100K
C1
C2
Real-Time Clock
RTC OSCILLATOR OPERATION
RTC INTERRUPTS
32.768 kHz
XTAL
R
RECOMMENDED
COMPONENTS FOR
TIMER1 LP OSCILLATOR
RTC
 2010 Microchip Technology Inc.
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