DSPIC30F4013-20I/PT Microchip Technology, DSPIC30F4013-20I/PT Datasheet - Page 94

• Manufacturer Part Number: DSPIC30F4013-20I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 30
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401320IPT

dsPIC30F3014/4013
14.4.2
Once addressed, the master can generate a Repeated
Start, reset the high byte of the address and set the
R_W bit without generating a Stop bit, thus initiating a
slave transmit operation.
14.5
In the Slave modes, the module can synchronize buffer
reads and write to the master device by clock stretching.
14.5.1
Both 10-Bit and 7-Bit Transmit modes implement clock
stretching by asserting the SCLREL bit after the falling
edge of the ninth clock, if the TBF bit is cleared,
indicating the buffer is empty.
In Slave Transmit modes, clock stretching is always
performed irrespective of the STREN bit.
Clock synchronization takes place following the ninth
clock of the transmit sequence. If the device samples
an ACK on the falling edge of the ninth clock and if the
TBF bit is still clear, then the SCLREL bit is automati-
cally cleared. The SCLREL being cleared to ‘0’ asserts
the SCL line low. The user’s ISR must set the SCLREL
bit before transmission is allowed to continue. By hold-
ing the SCL line low, the user has time to service the
ISR and load the contents of the I2CTRN before the
master device can initiate another transmit sequence.
14.5.2
The STREN bit in the I2CCON register can be used to
enable clock stretching in Slave Receive mode. When
the STREN bit is set, the SCL pin is held low at the end
of each data receive sequence.
14.5.3
When the STREN bit is set in Slave Receive mode, the
SCL line is held low when the buffer register is full. The
method for stretching the SCL output is the same for
both 7 and 10-Bit Addressing modes.
DS70138G-page 94
Note 1: If the user loads the contents of I2CTRN,
2: The SCLREL bit can be set in software,
Automatic Clock Stretch
10-BIT MODE SLAVE RECEPTION
TRANSMIT CLOCK STRETCHING
RECEIVE CLOCK STRETCHING
CLOCK STRETCHING DURING
7-BIT ADDRESSING (STREN = 1)
setting the TBF bit before the falling edge
of the ninth clock, the SCLREL bit is not
be cleared and clock stretching does not
occur.
regardless of the state of the TBF bit.
Clock stretching takes place following the ninth clock of
the receive sequence. On the falling edge of the ninth
clock at the end of the ACK sequence, if the RBF bit is
set, the SCLREL bit is automatically cleared, forcing
the SCL output to be held low. The user’s ISR must set
the SCLREL bit before reception is allowed to continue.
By holding the SCL line low, the user has time to ser-
vice the ISR and read the contents of the I2CRCV
before the master device can initiate another receive
sequence.
occurring.
14.5.4
Clock stretching takes place automatically during the
addressing sequence. Because this module has a
register for the entire address, it is not necessary for
the protocol to wait for the address to be updated.
After the address phase is complete, clock stretching
occurs on each data receive or transmit sequence, as
described earlier.
14.6
When the STREN bit is ‘1’, the SCLREL bit can be
cleared by software to allow software to control the
clock stretching. Program logic synchronizes writes to
the SCLREL bit with the SCL clock. Clearing the
SCLREL bit does not assert the SCL output until the
module detects a falling edge on the SCL output and
SCL is sampled low. If the SCLREL bit is cleared by the
user while the SCL line has been sampled low, the SCL
output is asserted (held low). The SCL output remains
low until the SCLREL bit is set and all other devices on
the I
write to the SCLREL bit does not violate the minimum
high time requirement for SCL.
If the STREN bit is ‘0’, a software write to the SCLREL
bit is disregarded and has no effect on the SCLREL bit.
Note 1: If the user reads the contents of the
2
C bus have deasserted SCL. This ensures that a
2: The SCLREL bit can be set in software
Software Controlled Clock
Stretching (STREN = 1)
CLOCK STRETCHING DURING
10-BIT ADDRESSING (STREN = 1)
I2CRCV, clearing the RBF bit before the
falling edge of the ninth clock, the
SCLREL bit is not cleared and clock
stretching does not occur.
regardless of the state of the RBF bit. The
user should be careful to clear the RBF
bit in the ISR before the next receive
sequence in order to prevent an overflow
condition.
This prevents buffer
 2010 Microchip Technology Inc.
overruns from