DSPIC30F4011-30I/PT Microchip Technology, DSPIC30F4011-30I/PT Datasheet - Page 109

• Manufacturer Part Number: DSPIC30F4011-30I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4011-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 1024 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401130IPT

16.0
The Serial Peripheral Interface (SPI™) module is a
synchronous serial interface. It is useful for communi-
cating with other peripheral devices, such as
EEPROMs, shift registers, display drivers and A/D
converters, or other microcontrollers. It is compatible
with Motorola’s SPI and SIOP interfaces.
16.1
The SPI module consists of a 16-bit shift register,
SPI1SR, used for shifting data in and out, and a buffer
register, SPI1BUF. A control register, SPI1CON,
configures the module. Additionally, a status register,
SPI1STAT, indicates various status conditions.
The serial interface consists of 4 pins: SDI1 (Serial Data
Input), SDO1 (Serial Data Output), SCK1 (Shift Clock
Input or Output), and SS1 (active-low Slave Select).
In Master mode operation, SCK1 is a clock output, but
in Slave mode, it is a clock input.
A series of eight (8) or sixteen (16) clock pulses shift
out bits from the SPI1SR to SDO1 pin, and simultane-
ously, shifts in data from SDI1 pin. An interrupt is gen-
erated when the transfer is complete and the
corresponding interrupt flag bit (SPI1IF) is set. This
interrupt can be disabled through an interrupt enable
bit (SPI1IE).
The receive operation is double-buffered. When a
complete byte is received, it is transferred from
SPI1SR to SPI1BUF.
If the receive buffer is full when new data is being
transferred from SPI1SR to SPI1BUF, the module will
set the SPIROV bit, indicating an overflow condition.
The transfer of the data from SPI1SR to SPI1BUF will
not be completed and the new data will be lost. The
module will not respond to SCL transitions while
SPIROV is ‘1’, effectively disabling the module until
SPI1BUF is read by user software.
© 2010 Microchip Technology Inc.
Note:
SPI™ MODULE
Operating Function Description
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
dsPIC30F Family Reference Manual
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
Transmit writes are also double-buffered. The user
writes to SPI1BUF. When the master or slave transfer
is completed, the contents of the shift register
(SPI1SR) is moved to the receive buffer. If any trans-
mit data has been written to the buffer register, the
contents of the transmit buffer are moved to SPI1SR.
The received data is thus placed in SPI1BUF and the
transmit data in SPI1SR is ready for the next transfer.
In Master mode, the clock is generated by prescaling
the system clock. Data is transmitted as soon as a
value is written to SPI1BUF. The interrupt is generated
at the middle of the transfer of the last bit.
In Slave mode, data is transmitted and received as
external clock pulses appear on SCK1. Again, the
interrupt is generated when the last bit is latched. If
SS1 control is enabled, then transmission and recep-
tion are enabled only when SS1 = low. The SDO1
output will be disabled in SS1 mode with SS1 high.
The clock provided to the module is (F
clock is then prescaled by the primary (PPRE<1:0>)
and secondary (SPRE<2:0>) prescale factors. The
CKE bit determines whether transmit occurs on transi-
tion from active clock state to Idle clock state, or vice
versa. The CKP bit selects the Idle state (high or low)
for the clock.
16.1.1
A control bit, MODE16 (SPI1CON<10>), allows the
module to communicate in either 16-bit or 8-bit mode.
16-bit operation is identical to 8-bit operation, except
that the number of bits transmitted is 16 instead of 8.
The user software must disable the module prior to
changing the MODE16 bit. The SPI module is reset
when the MODE16 bit is changed by the user.
A basic difference between 8-bit and 16-bit operation is
that the data is transmitted out of bit 7 of the SPI1SR
for 8-bit operation, and data is transmitted out of bit 15
of the SPI1SR for 16-bit operation. In both modes, data
is shifted into bit 0 of the SPI1SR.
16.1.2
A control bit, DISSDO, is provided to the SPI1CON
register to allow the SDO1 output to be disabled. This
will allow the SPI module to be connected in an input
only configuration. SDO1 can also be used for general
purpose I/O.
Note:
dsPIC30F4011/4012
Both the transmit buffer (SPI1TXB) and
the receive buffer (SPI1RXB) are mapped
to the same register address, SPI1BUF.
WORD AND BYTE
COMMUNICATION
SDO1 DISABLE
DS70135G-page 109
OSC
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