DSPIC30F4011-30I/PT Microchip Technology, DSPIC30F4011-30I/PT Datasheet - Page 156

• Manufacturer Part Number: DSPIC30F4011-30I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4011-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 1024 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401130IPT

dsPIC30F4011/4012
21.2.7
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by appropriately
programming the FCKSM<1:0> Configuration bits
(Clock Switch and Monitor Selection bits) in the F
device Configuration register. If the FSCM function is
enabled, the LPRC internal oscillator runs at all times
(except during Sleep mode) and is not subject to
control by the SWDTEN bit.
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
system clock over to the FRC oscillator. The user then
has the option to either attempt to restart the oscillator
or execute a controlled shutdown. The user may decide
to treat the trap as a warm Reset by simply loading the
Reset address into the oscillator fail trap vector. In this
event, the CF (Clock Fail) status bit (OSCCON<3>) is
also set whenever a clock failure is recognized.
In the event of a clock failure, the WDT is unaffected
and continues to run on the LPRC clock.
If the oscillator has a very slow start-up time coming
out of POR, BOR or Sleep, it is possible that the
PWRT timer will expire before the oscillator has
started. In such cases, the FSCM is activated. The
FSCM initiates a clock failure trap, and the
COSC<1:0> bits are loaded with the Fast RC (FRC)
oscillator selection. This effectively shuts off the
original oscillator that was trying to start.
The user may detect this situation and restart the
oscillator in the clock fail trap Interrupt Service Routine
(ISR).
Upon a clock failure detection, the FSCM module
initiates a clock switch to the FRC oscillator as follows:
1.
2.
3.
For the purpose of clock switching, the clock sources
are sectioned into four groups:
• Primary
• Secondary
• Internal FRC
• Internal LPRC
The user can switch between these functional groups
but cannot switch between options within a group. If the
primary group is selected, then the choice within the
group is always determined by the FPR<3:0>
Configuration bits.
DS70135G-page 156
The COSC<1:0> bits (OSCCON<13:12>) are
loaded with the FRC oscillator selection value.
CF bit is set (OSCCON<3>).
OSWEN control bit (OSCCON<0>) is cleared.
FAIL-SAFE CLOCK MONITOR
OSC
The OSCCON register holds the control and status bits
related to clock switching.
• COSC<1:0>: Read-only status bits always reflect
• NOSC<1:0>: Control bits which are written to
• LOCK: The LOCK status bit indicates a PLL lock.
• CF: Read-only status bit indicating if a clock fail
• OSWEN: Control bit changes from a ‘0’ to a ‘1’
If Configuration bits, FCKSM<1:0> = 1x, then the clock
switching and Fail-Safe Clock Monitor functions are
disabled. This is the default Configuration bit setting.
If clock switching is disabled, then the FOS<1:0> and
FPR<3:0> bits directly control the oscillator selection,
and the COSC<1:0> bits do not control the clock
selection. However, these bits do reflect the clock
source selection.
21.2.8
A write to the OSCCON register is intentionally made
difficult because it controls clock switching and clock
scaling.
To write to the OSCCON low byte, the following code
sequence must be executed without any other
instructions in between:
Byte Write is allowed for one instruction cycle. Write the
desired value or use bit manipulation instruction.
To write to the OSCCON high byte, the following
instructions must be executed without any other
instructions in between:
Byte Write is allowed for one instruction cycle. Write the
desired value or use bit manipulation instruction.
the current oscillator group in effect.
indicate the new oscillator group of choice.
- On POR and BOR, COSC<1:0> and
detect has occurred.
when a clock transition sequence is initiated.
Clearing the OSWEN control bit aborts a clock
transition in progress (used for hang-up
situations).
Note:
NOSC<1:0> are both loaded with the
Configuration bit values, FOS<1:0>.
Byte Write 0x46 to OSCCON low
Byte Write 0x57 to OSCCON low
Byte Write 0x78 to OSCCON high
Byte Write 0x9A to OSCCON high
The application should not attempt to
switch to a clock of frequency lower than
100 kHz when the Fail-Safe Clock Monitor
is enabled. If such clock switching is
performed, the device may generate an
oscillator fail trap and switch to the Fast
RC (FRC) oscillator.
PROTECTION AGAINST
ACCIDENTAL WRITES TO OSCCON
© 2010 Microchip Technology Inc.