DSPIC33FJ128GP802-E/SO Microchip Technology, DSPIC33FJ128GP802-E/SO Datasheet - Page 2

• Manufacturer Part Number: DSPIC33FJ128GP802-E/SO
• Description: IC DSPIC MCU/DSP 128K 28-SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP802-E/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b, D/A 4x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 10-chx10-bit|10-chx12-bit
• On-chip Dac: 2-chx16-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 1:
TABLE 2:
DS80443F-page 2
dsPIC33FJ128GP202
dsPIC33FJ128GP204
dsPIC33FJ128GP802
dsPIC33FJ128GP804
Note 1:
Note 1:
Module
UART
UART
UART
I
SPI
2
SPI
I
I
I
I
I
C™
2
2
2
2
2
2:
C
C
C
C
C
The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for detailed information on
Device and Revision IDs for your specific device.
Only those issues indicated in the last column apply to the current silicon revision.
Part Number
Frame Mode
High-Speed
SILICON DEVREV VALUES (CONTINUED)
SILICON ISSUE SUMMARY
SFR Writes
Addressing
Addressing
Addressing
Operation
Interrupts
Transmit
IR Mode
Feature
Mode
10-bit
10-bit
10-bit
—
—
Number
Item
10.
11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
The 16x baud clock signal on the BCLK pin is present only
when the module is transmitting.
When the UART is in 4x mode (BRGH = 1) and using two
Stop bits (STSEL = 1), it may sample the first Stop bit
instead of the second one.
The SPI Transmit Buffer Full (SPITBF) flag does not get
set immediately after writing to the buffer.
The SPI module will generate incorrect frame synchronization
pulses in Frame Master mode if FRMDLY = 1.
The BCL bit in I2CSTAT can only be cleared with Word
instructions, and can be corrupted with byte instructions
and bit operations.
When the I
using the same address bits (A10 and A9) as other I
devices, A10 and A9 bits may not work as expected.
When the I
an address of 0x102, the I2CxRCV register content for the
lower address byte is 0x01 rather than 0x02.
With the I
Interrupt Input functions (if any) associated with SCL and
SDA pins will not reflect the actual digital logic levels on
the pins.
The 10-bit slave does not set the RBF flag or load the
I2CxRCV register, on address match if the Least
Significant bits (LSbs) of the address are the same as the
7-bit reserved addresses.
After the ACKSTAT bit is set when receiving a NACK, it
may be cleared by the reception of a Start or Stop bit.
The UART error interrupt may not occur, or may occur at
an incorrect time, if multiple errors occur during a short
period of time.
2
C module enabled, the PORT bits and external
2
2
Device ID
C module is configured for 10-bit addressing
C module is configured as a 10-bit slave with
0x062D
0x062F
0x0625
0x0627
Issue Summary
(1)
0x3001
Revision ID for Silicon Revision
A1
© 2010 Microchip Technology Inc.
0x3002
A2
2
C
0x3002
A1 A2 A3 A4
A3
X
X
X
X
X
X
X
X
X
X
X
Revisions
Affected
X
X
X
X
X
X
X
X
X
X
X
0x3003
X
X
X
X
X
X
X
X
X
X
X
A4
(1)
(2)
X
X
X
X
X
X
X
X
X
X
X