DSPIC33FJ128MC506A-I/PT Microchip Technology, DSPIC33FJ128MC506A-I/PT Datasheet - Page 138

• Manufacturer Part Number: DSPIC33FJ128MC506A-I/PT
• Description: IC DSPIC MCU/DSP 128K 64-TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC506A-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJXXXMCX06A/X08A/X10A
REGISTER 8-2:
DS70594B-page 138
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-7
bit 6-0
Note 1:
FORCE
R/W-0
U-0
—
2:
(1)
The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced
DMA transfer is complete.
See Table 8-1 for a complete listing of IRQ numbers for all interrupt sources.
FORCE: Force DMA Transfer bit
1 = Force a single DMA transfer (Manual mode)
0 = Automatic DMA transfer initiation by DMA request
Unimplemented: Read as ‘0’
IRQSEL<6:0>: DMA Peripheral IRQ Number Select bits
0000000-1111111 = DMAIRQ0-DMAIRQ127 selected to be Channel DMAREQ
IRQSEL6
R/W-0
U-0
—
DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER
(2)
W = Writable bit
‘1’ = Bit is set
IRQSEL5
R/W-0
U-0
—
(2)
IRQSEL4
R/W-0
(1)
U-0
Preliminary
—
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
IRQSEL3
U-0
U-0
—
(2)
(2)
IRQSEL2
U-0
U-0
—
(2)
 2009 Microchip Technology Inc.
x = Bit is unknown
IRQSEL1
R/W-0
U-0
—
(2)
IRQSEL0
R/W-0
U-0
—
bit 8
bit 0
(2)