DSPIC33FJ64GP706-I/PT Microchip Technology, DSPIC33FJ64GP706-I/PT Datasheet - Page 23

IC DSPIC MCU/DSP 64K 64TQFP

DSPIC33FJ64GP706-I/PT

Manufacturer Part Number
DSPIC33FJ64GP706-I/PT
Description
IC DSPIC MCU/DSP 64K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ64GP706-I/PT

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
53
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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6.5
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
system clock over to the FRC oscillator. The application
program then can either attempt to restart the oscillator,
or execute a controlled shutdown. The trap can be
treated as a warm Reset by simply loading the Reset
address into the oscillator fail trap vector.
© 2005 Microchip Technology Inc.
Fail-Safe Clock Monitor (FSCM)
Preliminary
6.6
The Reset system combines all Reset sources and
controls the device Master Reset signal.
Device Reset sources include:
• POR: Power-on Reset
• BOR: Brown-out Reset
• SWR: RESET Instruction
• EXTR: MCLR Reset
• WDTR: Watchdog Timer Time-out Reset
• TRAPR: Trap Conflict
• IOPUWR: Attempted execution of an Illegal
Opcode, or Indirect Addressing, using an
Uninitialized W register
Reset System
dsPIC33F
DS70155C-page 21

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