DSPIC33FJ128MC506A-I/MR Microchip Technology, DSPIC33FJ128MC506A-I/MR Datasheet - Page 25

IC DSPIC MCU/DSP 128K 64-QFN

DSPIC33FJ128MC506A-I/MR

Manufacturer Part Number
DSPIC33FJ128MC506A-I/MR
Description
IC DSPIC MCU/DSP 128K 64-QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ128MC506A-I/MR

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Product
DSCs
Processor Series
DSPIC33F
Core
dsPIC
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
3.0
The dsPIC33FJXXXMCX06A/X08A/X10A CPU module
has a 16-bit (data) modified Harvard architecture with
an enhanced instruction set, including significant sup-
port for DSP. The CPU has a 24-bit instruction word
with a variable length opcode field. The Program Coun-
ter (PC) is 23 bits wide and addresses up to
4M x 24 bits of user program memory space. The actual
amount of program memory implemented varies by
device. A single-cycle instruction prefetch mechanism is
used to help maintain throughput and provides predict-
able execution. All instructions execute in a single cycle,
with the exception of instructions that change the pro-
gram flow, the double word move (MOV.D) instruction
and the table instructions. Overhead-free program loop
constructs are supported using the DO and REPEAT
instructions, both of which are interruptible at any point.
The
have sixteen, 16-bit working registers in the program-
mer’s model. Each of the working registers can serve
as a data, address or address offset register. The 16th
working register (W15) operates as a software Stack
Pointer (SP) for interrupts and calls.
The dsPIC33FJXXXMCX06A/X08A/X10A instruction
set has two classes of instructions: MCU and DSP.
These two instruction classes are seamlessly inte-
grated into a single CPU. The instruction set includes
many addressing modes and is designed for optimum
‘C’ compiler efficiency. For most instructions, the
dsPIC33FJXXXMCX06A/X08A/X10A
capable of executing a data (or program data) memory
read, a working register (data) read, a data memory
write and a program (instruction) memory read per
instruction cycle. As a result, three parameter instruc-
tions can be supported, allowing A + B = C operations
to be executed in a single cycle.
A block diagram of the CPU is shown in Figure 3-1
and
dsPIC33FJXXXMCX06A/X08A/X10A
Figure 3-2.
 2009 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
dsPIC33FJXXXMCX06A/X08A/X10A
the
2: Some registers and associated bits
CPU
of the dsPIC33FJXXXMCX06A/X08A/
X10A family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the informa-
tion in this data sheet, refer to Section 2.
“CPU” (DS70204) in the “dsPIC33F/
PIC24H
which is available from the Microchip web
site (www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
programmer’s
Family
dsPIC33FJXXXMCX06A/X08A/X10A
Reference
model
is
devices
shown
for
Manual”,
devices
Preliminary
are
the
in
3.1
The data space can be addressed as 32K words or
64 Kbytes, and is split into two blocks referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software bound-
ary checking overhead for DSP algorithms. Further-
more, the X AGU circular addressing can be used with
any of the MCU class of instructions. The X AGU also
supports Bit-Reversed Addressing to greatly simplify
input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program to data space mapping feature lets any
instruction access program space as if it were data
space.
The data space also includes 2 Kbytes of DMA RAM,
which is primarily used for DMA data transfers but may
be used as general purpose RAM.
3.2
The DSP engine features a high-speed, 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating accumu-
lators and a 40-bit bidirectional barrel shifter. The barrel
shifter is capable of shifting a 40-bit value up to 16 bits
right or left in a single cycle. The DSP instructions oper-
ate seamlessly with all other instructions and have
been designed for optimal real-time performance. The
MAC instruction and other associated instructions can
concurrently fetch two data operands from memory
while multiplying two W registers, and accumulating
and optionally saturating the result in the same cycle.
This instruction functionality requires that the RAM
memory data space be split for these instructions and
linear for all others. Data space partitioning is achieved
in a transparent and flexible manner through dedicating
certain working registers to each address space.
Data Addressing Overview
DSP Engine Overview
DS70594B-page 25

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