DSPIC33FJ128MC506A-I/MR Microchip Technology, DSPIC33FJ128MC506A-I/MR Datasheet - Page 267

• Manufacturer Part Number: DSPIC33FJ128MC506A-I/MR
• Description: IC DSPIC MCU/DSP 128K 64-QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC506A-I/MR

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Product: DSCs
• Processor Series: DSPIC33F
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 24-2:
 2009 Microchip Technology Inc.
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Base
Instr
#
BTSS
BTST
BTSTS
CALL
CLR
CLRWDT
COM
CP
CP0
CPB
CPSEQ
CPSGT
CPSLT
CPSNE
DAW
DEC
DEC2
DISI
DIV
DIVF
DO
ED
EDAC
Mnemonic
Assembly
INSTRUCTION SET OVERVIEW (CONTINUED)
BTSS
BTSS
BTST
BTST.C
BTST.Z
BTST.C
BTST.Z
BTSTS
BTSTS.C
BTSTS.Z
CALL
CALL
CLR
CLR
CLR
CLR
CLRWDT
COM
COM
COM
CP
CP
CP
CP0
CP0
CPB
CPB
CPB
CPSEQ
CPSGT
CPSLT
CPSNE
DAW
DEC
DEC
DEC
DEC2
DEC2
DEC2
DISI
DIV.S
DIV.SD
DIV.U
DIV.UD
DIVF
DO
DO
ED
EDAC
dsPIC33FJXXXMCX06A/X08A/X10A
f,#bit4
Ws,#bit4
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wb
Ws,Wb
f,#bit4
Ws,#bit4
Ws,#bit4
lit23
Wn
f
WREG
Ws
Acc,Wx,Wxd,Wy,Wyd,AWB
f
f,WREG
Ws,Wd
f
Wb,#lit5
Wb,Ws
f
Ws
f
Wb,#lit5
Wb,Ws
Wb, Wn
Wb, Wn
Wb, Wn
Wb, Wn
Wn
f
f,WREG
Ws,Wd
f
f,WREG
Ws,Wd
#lit14
Wm,Wn
Wm,Wn
Wm,Wn
Wm,Wn
#lit14,Expr
Wn,Expr
Wm*Wm,Acc,Wx,Wy,Wxd
Wm*Wm,Acc,Wx,Wy,Wxd
Assembly Syntax
Wm,Wn
Preliminary
Bit Test f, Skip if Set
Bit Test Ws, Skip if Set
Bit Test f
Bit Test Ws to C
Bit Test Ws to Z
Bit Test Ws<Wb> to C
Bit Test Ws<Wb> to Z
Bit Test then Set f
Bit Test Ws to C, then Set
Bit Test Ws to Z, then Set
Call Subroutine
Call Indirect Subroutine
f = 0x0000
WREG = 0x0000
Ws = 0x0000
Clear Accumulator
Clear Watchdog Timer
f = f
WREG = f
Wd = Ws
Compare f with WREG
Compare Wb with lit5
Compare Wb with Ws (Wb – Ws)
Compare f with 0x0000
Compare Ws with 0x0000
Compare f with WREG, with Borrow
Compare Wb with lit5, with Borrow
Compare Wb with Ws, with Borrow
Compare Wb with Wn, Skip if =
Compare Wb with Wn, Skip if >
Compare Wb with Wn, Skip if <
Compare Wb with Wn, Skip if 
Wn = Decimal Adjust Wn
f = f – 1
WREG = f – 1
Wd = Ws – 1
f = f – 2
WREG = f – 2
Wd = Ws – 2
Disable Interrupts for k Instruction Cycles
Signed 16/16-bit Integer Divide
Signed 32/16-bit Integer Divide
Unsigned 16/16-bit Integer Divide
Unsigned 32/16-bit Integer Divide
Signed 16/16-bit Fractional Divide
Do Code to PC + Expr, lit14 + 1 Times
Do Code to PC + Expr, (Wn) + 1 Times
Euclidean Distance (no accumulate)
Euclidean Distance
(Wb – Ws – C)
Description
Words
# of
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
Cycles
(2 or 3)
(2 or 3)
(2 or 3)
(2 or 3)
(2 or 3)
(2 or 3)
DS70594B-page 267
# of
18
18
18
18
18
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
OA,OB,SA,SB
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
Status Flags
WDTO,Sleep
OA,OB,OAB,
OA,OB,OAB,
SA,SB,SAB
SA,SB,SAB
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
Affected
None
None
None
None
None
None
None
None
None
None
None
None
None
None
N,Z
N,Z
N,Z
Z
C
Z
C
Z
Z
C
Z
C