IC DSPIC MCU/DSP 128K 100-TQFP

DSPIC33FJ128GP310A-I/PT

Manufacturer Part NumberDSPIC33FJ128GP310A-I/PT
DescriptionIC DSPIC MCU/DSP 128K 100-TQFP
ManufacturerMicrochip Technology
SeriesdsPIC™ 33F
DSPIC33FJ128GP310A-I/PT datasheet
 

Specifications of DSPIC33FJ128GP310A-I/PT

Program Memory TypeFLASHProgram Memory Size128KB (128K x 8)
Package / Case100-TFQFPCore ProcessordsPIC
Core Size16-BitSpeed40 MIPs
ConnectivityI²C, IrDA, LIN, SPI, UART/USARTPeripheralsAC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o85Ram Size16K x 8
Voltage - Supply (vcc/vdd)3 V ~ 3.6 VData ConvertersA/D 32x10b/12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
ProductDSCsData Bus Width16 bit
Processor SeriesDSPIC33FCoredsPIC
Maximum Clock Frequency40 MHzNumber Of Programmable I/os85
Data Ram Size16 KBMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By SupplierPG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033Minimum Operating Temperature- 40 C
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With876-1001 - DSPIC33 BREAKOUT BOARD
Eeprom Size-  
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Page 199/338

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dsPIC33FJXXXGPX06A/X08A/X10A
REGISTER 18-2:
U
STA: UART
x
bit 5
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect
0 = Address Detect mode disabled
bit 4
RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Receiver is active
bit 3
PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0 = Parity error has not been detected
bit 2
FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (character at the top of the receive
FIFO)
0 = Framing error has not been detected
bit 1
OERR: Receive Buffer Overrun Error Status bit (read/clear only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed. Clearing a previously set OERR bit (1  0 transition) will reset
the receiver buffer and the UxRSR to the empty state
bit 0
URXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for infor-
mation on enabling the UART module for transmit operation.
 2009 Microchip Technology Inc.
STATUS AND CONTROL REGISTER (CONTINUED)
x
Preliminary
DS70593B-page 199