DSPIC33FJ128GP706-I/PT Microchip Technology, DSPIC33FJ128GP706-I/PT Datasheet - Page 30

• Manufacturer Part Number: DSPIC33FJ128GP706-I/PT
• Description: IC DSPIC MCU/DSP 128K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP706-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 85
• Data Ram Size: 16 KB
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 4096 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP3909 / dsPIC33F 3-Phase Energy Meter Reference Design
DS51723A-page 30
Each block can be categorized into one of three types of calculations:
1. Calculation for an individual phase
2. Calculation for all 3 phases
3. Calculation of power accumulation (Energy)
3.3.1
The first blocks of the calculation flow are to determine how many samples to use for
the quasi-synchronization sampling algorithm. See Appendix C. “Power Calculation
Theory” for more information on this approach.
The firmware selects the proper quasi-synchronization window function (array of data)
and corresponding sine/cosine table according to the number of sampling points in
present current cycle.
The number of sampling points is obtained from the last calculation of frequency
function. As the line frequency fluctuates in slow motion and typically varies by a small
amount over three (3) line cycles, the period of line frequency measurements of the
previous cycle can be used to determine data length of sampling.
The quasi-synchronization window function is an array established in advance, and its
length is the same as that of the sampling data, which is obtained by the weight
coefficient multiplied by 32768. In this design, the method of quadrature by
complexification echelon is used, corresponding weight coefficient is calculated with
three (3) iterations. Three iterations implies that the length of the input original data is
equal to the number of sampling points in three cycles. The number of sampling points
in each cycle is usually different from the input signal cycle, but it will be close to an
integral multiple of the input signal cycle. For example, at a sampling rate of 3.2 ksps,
50 Hz input signal corresponds to 64 sampling points for each cycle, and 50.1 Hz input
signal would also be close to 64 sampling points for each cycle. Again, 51 Hz input
signal would be close to 63 sampling points for each cycle. Therefore, at different input
frequencies, the corresponding numbers of sampling points in each cycle are different.
Consequently, the corresponding quasi-sync window function and sine/cosine table
need to be established according to different numbers of sampling points. The
sine/cosine table is established by evenly dividing a cycle into a number of segments
equal to the number of sampling points, calculating corresponding sine/cosine values
and then multiplying the values by 32768. The purpose of the multiplication is to
change the original operation of floating point numbers into that of fixed-point numbers.
Adjustments will be performed in the final stage of calculation.
The processing of the original signal being processed by the quasi-synchronization
window function is actually a process of array multiplication, i.e. the original input signal
is multiplied with a corresponding array of window functions. It's accomplished by the
function qusi_syn_wnd(), which is written in assembly to take full advantages of DSP
features.
3.3.2
A Direct Fourier Transform (DFT) is performed on the collected sets of data. Process-
ing of the original signal by quasi-synchronization window can effectively reduce
spectrum leakage caused by non-entire-cycle sampling during DFT transformation.
The data length is not a power of 2, therefore, the FFT algorithm cannot be used in DFT
transformation. DFT transform is accomplished by function DFT(), which is written in
assembly to take full advantages of the DSP feature of accumulated multiplication.
Since an FFT algorithm cannot be used, and it takes longer to perform a DFT
calculation, this is the most time-consuming process in the entire system.
Process Quasi-Synchronization Window
DFT Transformation
© 2009 Microchip Technology Inc.