DSPIC33FJ128GP706-I/PT Microchip Technology, DSPIC33FJ128GP706-I/PT Datasheet - Page 33

• Manufacturer Part Number: DSPIC33FJ128GP706-I/PT
• Description: IC DSPIC MCU/DSP 128K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP706-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 85
• Data Ram Size: 16 KB
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 4096 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.4
FIGURE 3-3:
3.4.1
© 2009 Microchip Technology Inc.
ADC SAMPLING SCHEME FOR CALCULATIONS
Processing IC1 Interrupt
Sampling
Cycle n
Idle
The ADC conversion rate of the MCP3909 device is determined by the frequency of
master clock, MCLK, and the rate will be MCLK/256. After each conversion is complete,
a DataReady signal (4-CLK length) is generated by the SDO of the MCP3909 device.
The signal is fed into IC1 (Input Capture 1 on the dsPIC33F), allowing the Interrupt
Service Routine (ISR) of IC1 to invoke data-read function of the MCP3909 device.
When the MCP3909 device outputs data, it first sends the ADC result of the voltage
channel, then that of the current channel, with the MSB first.
The frequency of the master clock, MCLK, of the MCP3909 device is 3.2768 MHz, and
ADC outputs @12.8 ksps. In practice 6.4 ksps sampling rate is used in the program,
which means only 1 output data is used for every 2 data sampled. For a 50 Hz input
signal, a 6.4 ksps sampling rate will take 128 samples for each cycle. The active power
calculation is computed based on this condition.
The other parameters for which precision is not critical, such as reactive energy,
voltage, current and frequency, the sampling rate may be reduced to save data storage
space and processing time. In this design, the 3.2 ksps sampling rate is used, which
means only 1 result is stored for every 4 ADC conversions.
In the program, sampling and calculation are carried out concurrently, and data is
stored in the cyclic array in the dsPIC33F RAM. A calculation may be performed after
either 1 cycle, 2 cycles or 3 cycles of data are sampled, which can be configured in the
program. The user should note that frequent calculations will increase the measure-
ment precision at the price of system overhead and response speed, therefore making
proper tradeoffs based on practical requirement. In this design, 3 cycles of signals are
sampled before an AC electrical parameter calculation is performed. Refer to
Figure 3-3.
AC Signal Sampling alnd Computing.
Input capture IC1 is used to detect if the A/D conversion is complete. After each
conversion, a positive pulse the width of 4 clock cycles is outputted by the SDO pin of
the MCP3909 device. IC1 is used to detect the falling edge of the pulse and generate
an interrupt for every 2 falling edges, i.e., 1 data is read for every 2 conversions, thus
realizing 6.4 ksps sampling rate.
In addition to reading the data of the MCP3909 device, the IC1 interrupt service routine
(ISR) also controls the energy pulse output generation. Energy pulse processing
consists of active/reactive energy pulse processing. For the pulses to be outputted
more uniformly, the clock resolution used to generate the pulses must be as high as
possible. The interval of the IC1 interrupt is 156.25 µs, therefore, the resolution
generated by the pulse can be up to 156.25 µs.
Cycle n+1
Sampling
Idle
Cycle n+2
Sampling
Idle
n,n+1,n+2
Calculate
Cycle n+3
Sampling
Cycle n+4
Sampling
Idle
Firmware
DS51723A-page 33