DSPIC33FJ128GP706-I/PT Microchip Technology, DSPIC33FJ128GP706-I/PT Datasheet - Page 41

• Manufacturer Part Number: DSPIC33FJ128GP706-I/PT
• Description: IC DSPIC MCU/DSP 128K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP706-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 85
• Data Ram Size: 16 KB
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 4096 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.4
© 2009 Microchip Technology Inc.
PHASE LAG CALIBRATION
The phase lag calibration function is implemented by the upper computer by sending
the proper commands via the UART. When calibrating phase lag, error from the
calibration equipment and channel information to be adjusted are sent to the dsPIC33F
energy meter. When the front-end receives the command, it calls this module. The flow
is as follows:
1. Determine the phase to be calibrated according to parameters received.
2. Calculate new phase lag calibration coef. according to the error value received
3. Store the coefficient after correction into the EEPROM.
This meter design supports single, two, and five point calibration for phase lag error
correction.
The purpose of phase lag calibration is to eliminate the impact of phase lag introduced
by the current transformer (CT), and voltage transformer (PT) over the power measure-
ment range.
The voltage transformer usually has a constant load, thereby introducing a phase lag
that varies insignificantly. The dynamic range of current is larger, and under different
current loads, phase lags caused by CT vary greatly. In order to meet the requirements
of measurement accuracy in the entire range, it is usually necessary to segment the
phase lag and calibrate.
In this design, current is partitioned into 5 regions.
TABLE 4-1:
The partition limit for the current region can be modified in the header file of the
program. If accuracy is not critical, single-point calibration and two-point calibration can
be used to improve the efficiency of meter calibration.
Single, Two, or Five Point Calibration
Single-, two- or five-point calibration method can be configured by modifying the
header file. When using the single-point calibration, the phase lag compensation
values of all regions are the same; When using two-point calibration, the compensation
values of region 1 and 2 (0-0.075 I
compensation values for region 3, 4 and 5 (0.2 I
4.0 I
and the measured value.
B
) are the same.
Region
1
2
3
4
5
CURRENT REGIONS FOR PHASE CALIBRATION
B
, 0.075 I
B
- 0.2 I
Current Range
0.075 I
0.2 I
0.75 I
1.5 I
B
0 - 0.075 I
- 0.75 I
B
B
B
) are the same, and the phase lag
Meter Calibration
B
- 0.75 I
B
- 4.0 I
-1.5 I
- 0.2 I
B
B
, 0.75 I
B
B
B
B
B
- 1.5 I
DS51723A-page 41
B
, 1.5 I
B
-