DSPIC33FJ128GP706A-I/MR Microchip Technology, DSPIC33FJ128GP706A-I/MR Datasheet - Page 89

• Manufacturer Part Number: DSPIC33FJ128GP706A-I/MR
• Description: IC DSPIC MCU/DSP 128K 64-QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP706A-I/MR

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Product: DSCs
• Processor Series: DSPIC33F
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 53
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C.6
© 2009 Microchip Technology Inc.
IMPROVING MEASUREMENT PRECISION OF QUASI-SYNCHRONOUS
SAMPLING ALGORITHM
When using the quasi-synchronous sampling method for harmonic analysis and
calculation of power as well as voltage and current, strict restrictions apply for the
algorithm and compensation, (i.e., the frequency offset must not exceed 1% of the
central frequency). Precision of the result increases as the frequency offset gets less.
Measurement accuracy is not guaranteed, if this condition can not be met. Figure C-4
shows the quasi-synchronization algorithm using 3 iterations with input signal ranging
from 47.5 Hz to 52.5 Hz. The algorithm is for calculating the active power, the reactive
power and the relative error of current and voltage. Figure C-4 shows that the algorithm
works well when the frequency falls in the range of 47.5 Hz to 52.5 Hz. As the
frequency deviates from the range, the error increases significantly. Therefore, the
algorithm needs to be improved to fit into more applications with a more relaxed
restriction.
FIGURE C-4:
The quasi-sync sampling algorithm has relative high accuracy in frequency measure-
ment and the error can be less than 0.005 Hz. If the frequency range to be measured
can be segmented to make the frequency input closest to the multiple of cycle point,
and processed using appropriate quasi-sync window function and sine/cosine tale,
then the algorithm can be used for a much wider range of frequency .
Figure C-5 is the error analysis of the improved 3-iteration quasi-synchronous
algorithm at 3.2 ksps. It shows that the relative error for each result can be well
controlled when the frequency of the input signal falls in the range of 47.5 Hz to
52.5 Hz.
Figure C-5 clearly shows that the relative errors of the current, voltage, active power
and reactive power in the entire frequency range are less than 0.08%. Also, when the
input frequency is around the multiple of cycle frequencies (52.459 Hz, 51.613 Hz,
50.794 Hz, 50.0 Hz, 49.231 Hz, 48.485 Hz and 47.761 Hz), the calculateion error is
Quasi-sync Algorithm Error Analysis of 3 Iterations.
Power Calculation Theory
DS51723A-page 89