DSPIC33FJ128MC510A-I/PT Microchip Technology, DSPIC33FJ128MC510A-I/PT Datasheet - Page 255

• Manufacturer Part Number: DSPIC33FJ128MC510A-I/PT
• Description: IC DSPIC MCU/DSP 128K 100-TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC510A-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 100-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 85
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

23.0
dsPIC33FJXXXMCX06A/X08A/X10A devices include
several features intended to maximize application
flexibility and reliability, and minimize cost through
elimination of external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
TABLE 23-1:
 2009 Microchip Technology Inc.
0xF80000 FBS
0xF80002 FSS
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
Legend: — = unimplemented bit, reads as ‘0’.
Note 1:
Address
Note 1: This data sheet summarizes the features
2:
3:
2: Some registers and associated bits
SPECIAL FEATURES
These bits are reserved for use by development tools and must be programmed as ‘1’.
When read, this bit returns the current programmed value.
This bit is unimplemented on dsPIC33FJ64MCX06A/X08A/X10A and dsPIC33FJ128MCX06A/X08A/X10A
devices and reads as ‘0’.
of
dsPIC33FJXXXMCX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the informa-
tion in this data sheet, refer to Section
23.
(DS70199), Section 24. “Programming
and Diagnostics” (DS70207) and Sec-
tion
(DS70194) in the “dsPIC33F/PIC24H
Family Reference Manual”, which are
available from the Microchip web site
(www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to 4.0 “Memory
Organization” in this data sheet for
device-specific
information.
Name
DEVICE CONFIGURATION REGISTER MAP
25.
“CodeGuard™
dsPIC33FJXXXMCX06A/X08A/X10A
FWDTEN
“Device
PWMPIN
IESO
Bit 7
—
FCKSM<1:0>
register
Reserved
RBS<1:0>
RSS<1:0>
Configuration”
Reserved
WINDIS
HPOL
(1)
Bit 6
—
and
Security”
(2)
the
Preliminary
bit
PLLKEN
JTAGEN
LPOL
Bit 5
—
—
—
—
—
(3)
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
23.1
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 0xF80000.
The device Configuration register map is shown in
Table 23-1.
The individual Configuration bit descriptions for the
Configuration registers are shown in Table 23-2.
Note that address, 0xF80000, is beyond the user
program memory space. In fact, it belongs to the con-
figuration memory space (0x800000-0xFFFFFF) which
can only be accessed using table reads and table
writes.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
WDTPRE
Bit 4
—
—
—
—
—
—
—
Configuration Bits
Bit 3
—
—
—
—
—
BSS<2:0>
SSS<2:0>
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
GSS1
Bit 2
—
FNOSC<2:0>
FPWRT<2:0>
DS70594B-page 255
GSS0
Bit 1
ICS<1:0>
BWRP
SWRP
GWRP
Bit 0