DSPIC33FJ128MC510A-I/PT Microchip Technology, DSPIC33FJ128MC510A-I/PT Datasheet - Page 26

• Manufacturer Part Number: DSPIC33FJ128MC510A-I/PT
• Description: IC DSPIC MCU/DSP 128K 100-TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC510A-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 100-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 85
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

feature a 17-bit by 17-bit, single-cycle multiplier that is
multiplier can perform signed, unsigned and mixed sign
dsPIC33FJXXXMCX06A/X08A/X10A
3.3
The
shared by both the MCU ALU and DSP engine. The
multiplication. Using a 17-bit by 17-bit multiplier for 16-bit
by 16-bit multiplication not only allows you to perform
mixed sign multiplication, it also achieves accurate
results for special operations, such as (-1.0) x (-1.0).
FIGURE 3-1:
DS70594B-page 26
Control Block
PSV & Table
Data Access
dsPIC33FJXXXMCX06A/X08A/X10A
Program Memory
Special MCU Features
Address Latch
Data Latch
23
23
Controller
Interrupt
dsPIC33FJXXXMCX06A/X08A/X10A CPU CORE BLOCK DIAGRAM
23
to Various Blocks
Control Signals
Control
Stack
Logic
Instruction
Decode &
PCU
Program Counter
Control
24
8
PCH
Control
Logic
Loop
16
PCL
devices
Preliminary
Divide Support
DSP Engine
16
Y Data Bus
X Data Bus
Instruction Reg
Data Latch
ROM Latch
Address Generator Units
Address
X RAM
Latch
The
support 16/16 and 32/16 divide operations, both frac-
tional and integer. All divide instructions are iterative
operations. They must be executed within a REPEAT
loop, resulting in a total execution time of 19 instruction
cycles. The divide operation can be interrupted during
any of those 19 cycles without a loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
16
16
dsPIC33FJXXXMCX06A/X08A/X10A
Data Latch
W Register Array
Address
Y RAM
Latch
EA MUX
16 x 16
16
16
16
16-Bit ALU
16
16
 2009 Microchip Technology Inc.
16
16
Controller
DMA
RAM
DMA
To Peripheral Modules
devices
16