DSPIC33FJ128GP310A-I/PF Microchip Technology, DSPIC33FJ128GP310A-I/PF Datasheet - Page 56

• Manufacturer Part Number: DSPIC33FJ128GP310A-I/PF
• Description: IC DSPIC MCU/DSP 128K 100-TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP310A-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 85
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 4-11:
TABLE 4-12:
TABLE 4-13:
TABLE 4-14:
SFR Name
U1MODE
U1STA
U1TXREG
U1RXREG
U1BRG
Legend:
U2MODE
U2STA
U2TXREG
U2RXREG
U2BRG
Legend:
SPI1STAT
SPI1CON1
SPI1CON2
SPI1BUF
Legend:
SPI2STAT
SPI2CON1
SPI2CON2
SPI2BUF
Legend:
SFR Name
Name
Name
SFR
SFR
Addr
Addr
Addr
Addr
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SFR
0230
0232
0234
0236
0238
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0240
0242
0244
0248
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SFR
0260
0262
0264
0268
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0220
0222
0224
0226
0228
SFR
SFR
UTXISEL1
FRMEN
UART1 REGISTER MAP
UART2 REGISTER MAP
UARTEN
SPI1 REGISTER MAP
SPI2 REGISTER MAP
SPIEN
UTXISEL1
FRMEN
Bit 15
SPIEN
UARTEN
Bit 15
Bit 15
—
Bit 15
—
—
—
—
—
SPIFSD
Bit 14
UTXINV
SPIFSD
UTXINV UTXISEL0
Bit 14
Bit 14
Bit 14
—
—
—
—
—
—
—
—
—
—
UTXISEL0
FRMPOL
SPISIDL
Bit 13
FRMPOL
Bit 13
USIDL
SPISIDL
Bit 13
USIDL
Bit 13
—
—
—
—
—
—
DISSCK
Bit 12
Bit 12
DISSCK
Bit 12
IREN
IREN
Bit 12
—
—
—
—
—
—
—
—
—
—
DISSDO
UTXBRK
UTXBRK
RTSMD
RTSMD
Bit 11
Bit 11
DISSDO
Bit 11
Bit 11
—
—
—
—
—
—
—
—
MODE16
UTXEN
UTXEN
MODE16
Bit 10
Bit 10
Bit 10
Bit 10
—
—
—
—
—
—
—
—
—
—
SPI2 Transmit and Receive Buffer Register
UTXBF
SPI1 Transmit and Receive Buffer Register
UEN1
UTXBF
Bit 9
UEN1
Bit 9
Bit 9
SMP
—
—
Bit 9
SMP
—
—
—
—
—
—
Baud Rate Generator Prescaler
Baud Rate Generator Prescaler
UEN0
TRMT
TRMT
Bit 8
UEN0
Bit 8
Bit 8
CKE
Bit 8
CKE
—
—
—
—
WAKE
WAKE
Bit 7
Bit 7
SSEN
URXISEL<1:0>
URXISEL<1:0>
Bit 7
SSEN
Bit 7
—
—
—
—
LPBACK
LPBACK
SPIROV
SPIROV
Bit 6
Bit 6
Bit 6
CKP
Bit 6
CKP
—
—
ABAUD
ADDEN
ABAUD
ADDEN
MSTEN
MSTEN
Bit 5
Bit 5
Bit 5
Bit 5
UART Transmit Register
UART Receive Register
—
—
UART Transmit Register
—
—
UART Receive Register
URXINV
URXINV
RIDLE
RIDLE
Bit 4
Bit 4
Bit 4
Bit 4
—
—
—
—
SPRE<2:0>
SPRE<2:0>
BRGH
PERR
BRGH
PERR
Bit 3
Bit 3
Bit 3
Bit 3
—
—
—
—
FERR
FERR
Bit 2
Bit 2
Bit 2
Bit 2
PDSEL<1:0>
PDSEL<1:0>
—
—
—
—
FRMDLY
FRMDLY
OERR
OERR
SPITBF
SPITBF
Bit 1
Bit 1
Bit 1
Bit 1
PPRE<1:0>
PPRE<1:0>
URXDA
URXDA
STSEL
STSEL
SPIRBF
SPIRBF
Bit 0
Bit 0
Bit 0
Bit 0
—
—
Resets
Resets
Resets
Resets
0000
0110
xxxx
0000
0000
0000
0110
xxxx
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
All
All
All
All