IC PIC MCU FLASH 8KX14 44TQFP

 

PIC16LF877A-I/PT

Manufacturer Part NumberPIC16LF877A-I/PT
DescriptionIC PIC MCU FLASH 8KX14 44TQFP
ManufacturerMicrochip Technology
SeriesPIC® 16F
PIC16LF877A-I/PT datasheets

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Specifications of PIC16LF877A-I/PT

Program Memory TypeFLASHProgram Memory Size14KB (8K x 14)
Package / Case44-TQFP, 44-VQFPCore ProcessorPIC
Core Size8-BitSpeed10MHz
ConnectivityI²C, SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, WDT
Number Of I /o33Eeprom Size256 x 8
Ram Size368 x 8Voltage - Supply (vcc/vdd)2 V ~ 5.5 V
Data ConvertersA/D 8x10bOscillator TypeExternal
Operating Temperature-40°C ~ 85°CProcessor SeriesPIC16LF
CorePICData Bus Width8 bit
Data Ram Size368 BInterface TypeI2C/SPI/USART
Maximum Clock Frequency20 MHzNumber Of Programmable I/os33
Number Of Timers3Operating Supply Voltage2 V to 5.5 V
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development Tools52715-96, 52716-328, 52717-734Development Tools By SupplierPG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
Minimum Operating Temperature- 40 COn-chip Adc8-ch x 10-bit
Package44TQFPDevice CorePIC
Family NamePIC16Maximum Speed20 MHz
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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PIC16F873A-ISO PDF datasheetPIC16F873A-ISO PDF datasheet #2
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Page 117/234

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10.2
USART Asynchronous Mode
In this mode, the USART uses standard Non-Return-
to-Zero (NRZ) format (one Start bit, eight or nine data
bits and one Stop bit). The most common data format
is 8 bits. An on-chip, dedicated, 8-bit Baud Rate
Generator can be used to derive standard baud rate
frequencies from the oscillator. The USART transmits
and receives the LSb first. The transmitter and receiver
are functionally independent but use the same data
format and baud rate. The baud rate generator
produces a clock, either x16 or x64 of the bit shift rate,
depending on bit BRGH (TXSTA<2>). Parity is not
supported by the hardware but can be implemented in
software (and stored as the ninth data bit).
Asynchronous mode is stopped during Sleep.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the
following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
10.2.1
USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 10-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer, TXREG.
The TXREG register is loaded with data in software.
The TSR register is not loaded until the Stop bit has
been transmitted from the previous load. As soon as
the Stop bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one T
), the TXREG register is empty and
CY
flag bit, TXIF (PIR1<4>), is set. This interrupt can be
FIGURE 10-1:
USART TRANSMIT BLOCK DIAGRAM
TXIF
TXIE
MSb
(8)
Interrupt
TXEN
Baud Rate CLK
SPBRG
Baud Rate Generator
 2003 Microchip Technology Inc.
enabled/disabled by setting/clearing enable bit, TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit, TRMT (TXSTA<1>),
shows the status of the TSR register. Status bit TRMT
is a read-only bit which is set when the TSR register is
empty. No interrupt logic is tied to this bit so the user
has to poll this bit in order to determine if the TSR
register is empty.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set. TXIF is cleared by loading TXREG.
Transmission is enabled by setting enable bit, TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the Baud Rate Generator (BRG) has produced a
shift clock (Figure 10-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immedi-
ate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 10-3).
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. As a result, the RC6/TX/CK pin will revert
to high-impedance.
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
Data Bus
TXREG Register
8
LSb
Pin Buffer
0
and Control
TSR Register
TRMT
TX9
TX9D
PIC16F87XA
RC6/TX/CK pin
SPEN
DS39582B-page 115

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