MCU AVR 128K ISP FLASH 40-PDIP

ATMEGA1284P-PU

Manufacturer Part NumberATMEGA1284P-PU
DescriptionMCU AVR 128K ISP FLASH 40-PDIP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA1284P-PU datasheets
 

Specifications of ATMEGA1284P-PU

Core ProcessorAVRCore Size8-Bit
Speed20MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size16K x 8
Voltage - Supply (vcc/vdd)1.8 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case40-DIP (0.600", 15.24mm)Processor SeriesATMEGA128x
CoreAVR8Data Bus Width8 bit
Data Ram Size16 KBInterface Type2-Wire/SPI/USART
Maximum Clock Frequency20 MHzNumber Of Programmable I/os32
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleThrough Hole3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 10-bitController Family/seriesAVR MEGA
No. Of I/o's32Eeprom Memory Size4KB
Ram Memory Size16KBCpu Speed20MHz
Rohs CompliantYesFor Use WithATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Features
High-performance, Low-power AVR
Advanced RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
– 16/32/64/128K Bytes of In-System Self-programmable Flash program memory
– 512B/1K/2K/4K Bytes EEPROM
– 1/2/4/16K Bytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
– Data retention: 20 years at 85°C/ 100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel, 10-bit ADC
Differential mode with selectable gain at 1x, 10x or 200x
– Byte-oriented Two-wire Serial Interface
– Two Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and
Extended Standby
I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF
– 44-pad DRQFN
– 49-ball VFBGA
Operating Voltages
– 1.8 - 5.5V
Speed Grades
– 0 - 4 MHz @ 1.8 - 5.5V
0 - 10 MHz @ 2.7 - 5.5V
0 - 20 MHz @ 4.5 - 5.5V
Power Consumption at 1 MHz, 1.8V, 25°C
– Active: 0.4 mA
– Power-down Mode: 0.1µA
– Power-save Mode: 0.6µA (Including 32 kHz RTC)
Note:
1. See
”Data Retention” on page 9
®
8-bit Microcontroller
(1)
for details.
8-bit
Microcontroller
with
16/32/64/128K
Bytes In-System
Programmable
Flash
ATmega164A
ATmega164PA
ATmega324A
ATmega324PA
ATmega644A
ATmega644PA
ATmega1284
ATmega1284P
8272A–AVR–01/10

ATMEGA1284P-PU Summary of contents

  • Page 1

    ... Power-down Mode: 0.1µA – Power-save Mode: 0.6µA (Including 32 kHz RTC) Note: 1. See ”Data Retention” on page 9 ® 8-bit Microcontroller (1) for details. 8-bit Microcontroller with 16/32/64/128K Bytes In-System Programmable Flash ATmega164A ATmega164PA ATmega324A ATmega324PA ATmega644A ATmega644PA ATmega1284 ATmega1284P 8272A–AVR–01/10 ...

  • Page 2

    Pin Configurations 1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF for Figure 1-1. Note: 8272A–AVR–01/10 ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Pinout (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT15/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 ...

  • Page 3

    Pinout - DRQFN for ATmega164A/164PA/324A/324PA Figure 1- Table 1- 8272A–AVR–01/10 DRQFN - Pinout Top view B1 B15 B2 B14 B3 B13 ...

  • Page 4

    Pinout - VFBGA for ATmega164A/164PA/324A/324PA Figure 1- Table 1- 8272A–AVR–01/10 VFBGA - Pinout Top view BGA - ...

  • Page 5

    Overview The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instruc- tions in a single clock cycle, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P achieves throughputs approaching 1 MIPS per MHz allowing the system ...

  • Page 6

    ... C compilers, macro assemblers, pro- gram debugger/simulators, in-circuit emulators, and evaluation kits. 2.2 Comparison Between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P Table 2-1. Differences between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P ...

  • Page 7

    Pin Descriptions 2.3.1 VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7:PA0) Port A serves as analog inputs to the Analog-to-digital Converter. Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors ...

  • Page 8

    RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Characteristics” on page 2.3.8 ...

  • Page 9

    ... Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling compiler dependent ...

  • Page 10

    AVR CPU Core 6.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, ...

  • Page 11

    ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as ...

  • Page 12

    Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine ...

  • Page 13

    General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit ...

  • Page 14

    The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, ...

  • Page 15

    ... Initial values respectively for the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Stack Pointer size Device ATmega164A/ATmega164PA ATmega324A/ATmega324PA ATmega644A/ATmega644PA ATmega1284/ATmega1284P , directly generated from the selected clock source for the CPU shows the parallel instruction fetches and instruction executions enabled The Parallel Instruction Fetches and Instruction Executions T1 clk ...

  • Page 16

    Figure 6-5. Register Operands Fetch ALU Operation Execute 6.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All ...

  • Page 17

    When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt ...

  • Page 18

    If an interrupt occurs when the MCU is in sleep mode, the interrupt exe- cution response time is increased by five clock ...

  • Page 19

    AVR Memories 7.1 Overview ...

  • Page 20

    Figure 7-1. 7.3 SRAM Data Memory Figure 7-2 Memory is organized. The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. ...

  • Page 21

    The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and ...

  • Page 22

    EEPROM Data Memory ...

  • Page 23

    I/O Memory The I/O space definition of the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is shown in All ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between ...

  • Page 24

    Register Description 7.6.1 EEARH and EEARL – The EEPROM Address Register Bit 0x22 (0x42) 0x21 (0x41) Read/Write Initial Value • Bits 15:12 – Res: Reserved Bits These bits are reserved bits in the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P and will always read ...

  • Page 25

    The Programming times for the different modes are shown in While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table ...

  • Page 26

    When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU ...

  • Page 27

    The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glob- ally) so that no interrupts will occur during execution of these ...

  • Page 28

    The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example ...

  • Page 29

    GPIOR2 – General Purpose I/O Register 2 Bit 0x2B (0x4B) Read/Write Initial Value 7.6.5 GPIOR1 – General Purpose I/O Register 1 Bit 0x2A (0x4A) Read/Write Initial Value 7.6.6 GPIOR0 – General Purpose I/O Register 0 Bit 0x1E (0x3E) ...

  • Page 30

    System Clock and Clock Options 8.1 Clock Systems and their Distribution Figure 8-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by ...

  • Page 31

    Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. 8.1.4 Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the ...

  • Page 32

    Table 8-2. Typ Time-out (V Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The delay will not monitor the ...

  • Page 33

    Low Power Crystal Oscillator This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 out- put. It gives the lowest power consumption, but is not capable of driving other clock inputs, and may ...

  • Page 34

    Table 8-4. Oscillator Source / Power Conditions Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: 8.4 Full Swing Crystal Oscillator This Crystal Oscillator is a full swing oscillator, with rail-to-rail swing on ...

  • Page 35

    Table 8-6. Oscillator Source / Power Conditions Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: 8.5 Low Frequency Crystal Oscillator The Low-frequency ...

  • Page 36

    optional external capacitors as described the pin capacitance the load capacitance for a 32.768 kHz crystal specified by the crystal vendor the total stray ...

  • Page 37

    Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the the user. See 27-10 on page 334 The ...

  • Page 38

    Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre- quency is nominal at 3V and 25°C. This clock may be select as the system clock ...

  • Page 39

    Table 8-14. Table 8-15. Power Conditions BOD enabled Fast rising power Slowly rising power When applying an external clock required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the MCU. ...

  • Page 40

    System Clock Prescaler The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has a system clock prescaler, and the system clock can be divided by setting the 41. This feature can be used to decrease the system clock frequency and the power consump- tion when ...

  • Page 41

    Register Description 8.12.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write Initial Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations ...

  • Page 42

    The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 ...

  • Page 43

    Power Management and Sleep Modes 9.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby saving- power. The AVR provides various sleep modes allowing the user to tailor the power consumption to ...

  • Page 44

    BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, the BOD is actively monitoring the power supply voltage during a sleep period. To save power possible to disable the BOD by software ...

  • Page 45

    Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power- down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2- wire Serial Interface, and ...

  • Page 46

    Power Reduction Register The Power Reduction Register(PRR), see vides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read ...

  • Page 47

    Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In ...

  • Page 48

    Register Description 9.12.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 0x33 (0x53) Read/Write Initial Value • Bits – SM2:0: Sleep Mode Select Bits 2, ...

  • Page 49

    MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value Note: • Bit 6 – BODS: BOD Sleep The BODS bit must be written to logic one in order to turn off BOD during sleep, see on ...

  • Page 50

    Bit 3 - PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. • Bit 2 - PRSPI: Power Reduction ...

  • Page 51

    System Control and Reset 10.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a ...

  • Page 52

    Figure 10-1. Reset Logic BODLEVEL [2..0] 10.1.2 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be used ...

  • Page 53

    Figure 10-2. MCU Start-up, RESET Tied to V TIME-OUT INTERNAL Figure 10-3. MCU Start-up, RESET Extended Externally TIME-OUT INTERNAL 10.1.3 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than ...

  • Page 54

    Brown-out Detection ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has an On-chip Brown-out Detec- tion (BOD) circuit for monitoring the V level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike ...

  • Page 55

    Internal Voltage Reference ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P features an internal bandgap ref- erence. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 10.2.1 Voltage Reference Enable Signals and ...

  • Page 56

    Watchdog Timer 10.3.1 Features • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always ...

  • Page 57

    In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next ...

  • Page 58

    Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, ...

  • Page 59

    Register Description 10.4.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 0x34 (0x54) Read/Write Initial Value • Bit 4 – JTRF: JTAG Reset Flag This bit ...

  • Page 60

    WDTCSR – Watchdog Timer Control Register Bit (0x60) Read/Write Initial Value • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config- ured ...

  • Page 61

    Bit 5, 2:0 - WDP3:0: Watchdog Timer Prescaler and 0 The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run- ning. The different prescaling values and their corresponding time-out periods are ...

  • Page 62

    Interrupts 11.1 Overview ...

  • Page 63

    Table 11-1. Vector No Notes: Table 11-2 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. ...

  • Page 64

    When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8K bytes and the IVSEL ...

  • Page 65

    RESET: ldi 0x1F001 0x1F002 0x1F003 0x1F004 0x1F005 When the BOOTRST Fuse is programmed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before ...

  • Page 66

    Register Description 11.3.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value Note: • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start ...

  • Page 67

    Assembly Code Example Move_interrupts: C Code Example void Move_interrupts(void) { uchar temp; } 8272A–AVR–01/10 ; Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to ...

  • Page 68

    External Interrupts 12.1 Overview The External Interrupts are triggered by the INT2:0 pin or any of the PCINT31:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2:0 or PCINT31:0 pins are configured as outputs. ...

  • Page 69

    If low level interrupt is selected, the low level must be held until the com- pletion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request ...

  • Page 70

    PCICR – Pin Change Interrupt Control Register Bit (0x68) Read/Write Initial Value • Bit 3 – PCIE3: Pin Change Interrupt Enable 3 When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is ...

  • Page 71

    Bit 1 – PCIF1: Pin Change Interrupt Flag 1 When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set ...

  • Page 72

    PCMSK0 – Pin Change Mask Register 0 Bit (0x6B) Read/Write Initial Value • Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7..0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If ...

  • Page 73

    I/O-Ports 13.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin ...

  • Page 74

    Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 13.2 Ports as General Digital I/O The ports are bi-directional I/O ...

  • Page 75

    If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port ...

  • Page 76

    Figure 13-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when ...

  • Page 77

    Assembly Code Example C Code Example unsigned char i; Note: 13.2.5 Digital Input Enable and Sleep Modes As shown in schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save ...

  • Page 78

    Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing ...

  • Page 79

    Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. shows how the port pin control signals from the simplified ridden by alternate functions. The overriding signals may not be present in ...

  • Page 80

    Table 13-2 ure 13-5 in the modules having the alternate function. Table 13-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate ...

  • Page 81

    Alternate Functions of Port A The Port A pins with alternate functions are shown in Table 13-3. Port Pin PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 • ADC7:0/PCINT7:0 – Port A, Bit 7:0 ADC7:0, Analog to Digital ...

  • Page 82

    Table 13-4 on page 82 overriding signals shown in Table 13-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 13-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 8272A–AVR–01/10 and ...

  • Page 83

    Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 13-6. Port Pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 The alternate pin configuration is as follows: • SCK/PCINT15 – Port ...

  • Page 84

    MOSI/PCINT13 – Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. ...

  • Page 85

    T0/XCK0/PCINT8, Bit 0 T0, Timer/Counter0 counter source. XCK0, USART0 External clock. The Data Direction Register (DDB0) controls whether the clock is output (DDD0 set “one”) or input (DDD0 cleared). The XCK0 pin is active only when the USART0 ...

  • Page 86

    Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 13-9. Port Pin PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 • TOSC2/PCINT23 – Port C, Bit7 TOSC2, Timer Oscillator pin 2. ...

  • Page 87

    TMS/PCINT19 – Port C, Bit 3 TMS, JTAG Test Mode Select. PCINT19, Pin Change Interrupt source 19: The PC3 pin can serve as an external interrupt source. • TCK/PCINT18 – Port C, Bit 2 TCK, JTAG Test Clock. ...

  • Page 88

    Table 13-11. Overriding Signals for Alternate Functions in PC3:PC0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 13.3.4 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 13-12. ...

  • Page 89

    The alternate pin configuration is as follows: • OC2A/PCINT31 – Port D, Bit 7 OC2A, Output Compare Match A output: The PD7 pin can serve as an external output for the Timer/Counter2 Output Compare A. The pin has to ...

  • Page 90

    INT0/RXD1/PCINT26 – Port D, Bit 2 INT0, External Interrupt source 0. The PD2 pin can serve as an external interrupt source to the MCU. RXD1, RXD0, Receive Data (Data input pin for the USART1). When the USART1 receiver ...

  • Page 91

    Table 13-14. Overriding Signals for Alternate Functions in PD3:PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: 8272A–AVR–01/10 PD3/INT1/TXD1/ PD2/INT0/RXD1/ PCINT27 PCINT26 TXEN1 RXEN1 0 PORTD2 • PUD TXEN1 RXEN1 1 0 TXEN1 0 ...

  • Page 92

    Register Description 13.3.5 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value Note: • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if ...

  • Page 93

    PORTC – Port C Data Register Bit 0x08 (0x28) Read/Write Initial Value 13.3.13 DDRC – Port C Data Direction Register Bit 0x07 (0x27) Read/Write Initial Value 13.3.14 PINC – Port C Input Pins Address Bit 0x06 (0x26) Read/Write ...

  • Page 94

    Timer/Counter0 with PWM 14.1 Features • Two Independent Output Compare Units • Double Buffered Output Compare Registers • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM ...

  • Page 95

    The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output Compare Registers (OCR0A ...

  • Page 96

    Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 ...

  • Page 97

    Figure 14-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering ...

  • Page 98

    Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way ...

  • Page 99

    Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1 tells the Waveform Generator that no action on the OC0x ...

  • Page 100

    Figure 14-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can ...

  • Page 101

    PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Com- pare Matches between OCR0x and TCNT0. Figure 14-6. Fast ...

  • Page 102

    OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. 14.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 ...

  • Page 103

    OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See be visible on the port pin if the data direction for the port ...

  • Page 104

    Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 14-10 mode and PWM mode, where OCR0A is TOP. Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk clk (clk TCNTn OCRnx ...

  • Page 105

    Register Description 14.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both ...

  • Page 106

    Table 14-4. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B ...

  • Page 107

    Table 14-7 on page 107 to phase correct PWM mode. Table 14-7. COM0B1 Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved bits in the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P and will always read as zero. ...

  • Page 108

    TCCR0B – Timer/Counter Control Register B Bit 0x25 (0x45) Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring ...

  • Page 109

    Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 14-9. CS02 external pin modes are used ...

  • Page 110

    OCR0B – Output Compare Register B Bit 0x28 (0x48) Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an ...

  • Page 111

    Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output Compare Register0 B. OCF0B is cleared by ...

  • Page 112

    Timer/Counter1 with PWM 15.1 Features • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear ...

  • Page 113

    Figure 15-1. 16-bit Timer/Counter Block Diagram Note: 15.2.1 Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg- ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures ...

  • Page 114

    See Section “15.7” on page Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input ...

  • Page 115

    Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNTn value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two ...

  • Page 116

    The following code examples show how atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNTn: C Code Example ...

  • Page 117

    The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNTn: C Code Example ...

  • Page 118

    Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 Figure 15-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is ...

  • Page 119

    The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 15.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that ...

  • Page 120

    TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is ...

  • Page 121

    I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt handler is used). 15.7 Output Compare Units The 16-bit comparator continuously ...

  • Page 122

    PWM pulses, thereby making the out- put glitch-free. The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx ...

  • Page 123

    Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the ...

  • Page 124

    Compare Output Mode and Waveform Generation The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COMnx1 tells the Waveform Generator that no action on the OCnx ...

  • Page 125

    The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. Figure 15-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt ...

  • Page 126

    PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capaci- ...

  • Page 127

    ICRn value written is lower than the current value of TCNTn. The result will then be that the counter ...

  • Page 128

    However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined ...

  • Page 129

    OCRnx Registers are written. As the third period shown in TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of ...

  • Page 130

    OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches ...

  • Page 131

    Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is ...

  • Page 132

    Figure 15-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f Figure 15-12 frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 ...

  • Page 133

    Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 15.11 Register Description 15.11.1 TCCR1A – Timer/Counter1 Control Register A Bit (0x80) Read/Write Initial Value • Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit ...

  • Page 134

    Table 15-3 on page 134 the fast PWM mode. Table 15-3. COMnA1/COMnB1 Note: Table 15-4 on page 134 the phase correct or the phase and frequency correct, PWM mode. Table 15-4. COMnA1/COMnB1 Note: • Bit 1:0 – WGMn1:0: Waveform ...

  • Page 135

    Table 15-5. Waveform Generation Mode Bit Description WGMn2 WGMn1 Mode WGMn3 (CTCn) (PWMn1 ...

  • Page 136

    When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – ...

  • Page 137

    A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB bits are always read as zero. 15.11.4 TCNT1H and TCNT1L –Timer/Counter1 ...

  • Page 138

    ICR1H and ICR1L – Input Capture Register 1 Bit (0x87) (0x86) Read/Write Initial Value The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog ...

  • Page 139

    Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (See ...

  • Page 140

    Timer/Counter2 with PWM and Asynchronous Operation 16.1 Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler • Overflow ...

  • Page 141

    Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg- isters. Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the ...

  • Page 142

    Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 16-2 shows a block diagram of the counter and its surrounding environment. Figure 16-2. Counter Unit Block Diagram Signal description (internal signals): count ...

  • Page 143

    WGM22:0 bits and Compare Output mode (COM2x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of ...

  • Page 144

    Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of ...

  • Page 145

    Register bit for the OC2x pin (DDR_OC2x) must be set as output before the OC2x value is visi- ble on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare ...

  • Page 146

    The timing diagram for the CTC mode is shown in (TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then coun- ter (TCNT2) is cleared. Figure 16-5. CTC Mode, Timing Diagram TCNTn OCnx (Toggle) Period An ...

  • Page 147

    DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. ...

  • Page 148

    A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum frequency ...

  • Page 149

    In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2x1:0 ...

  • Page 150

    Figure 16-8. Timer/Counter Timing Diagram, no Prescaling clk clk (clk TCNTn TOVn Figure 16-9 on page 150 Figure 16-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 16-10 on page 150 Figure 16-10. Timer/Counter Timing ...

  • Page 151

    Figure 16-11 on page 151 Figure 16-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- (clk TCNTn (CTC) OCRnx OCFnx 16.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: ...

  • Page 152

    OCR2xUB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up. • If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise ...

  • Page 153

    Timer/Counter Prescaler Figure 16-12. Prescaler for Timer/Counter2 The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is ...

  • Page 154

    Register Description 16.11.1 TCCR2A – Timer/Counter Control Register A Bit (0xB0) Read/Write Initial Value • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of ...

  • Page 155

    Table 16-4 rect PWM mode. Table 16-4. COM2A1 Note: • Bits 5:4 – COM2B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 ...

  • Page 156

    Table 16-7 rect PWM mode. Table 16-7. COM2B1 Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved bits in the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P and will always read as zero. • Bits 1:0 – WGM21:0: ...

  • Page 157

    Read/Write Initial Value • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set ...

  • Page 158

    Table 16-9. CS22 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software ...

  • Page 159

    Bit 6 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buf- fer is enabled and an external clock can be input on Timer Oscillator 1 ...

  • Page 160

    Initial Value • Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is ...

  • Page 161

    GTCCR – General Timer/Counter Control Register Bit 0x23 (0x43) Read/Write Initial Value • Bit 7 - TSM: Timer/Counter Synchronization mode Writing the TSM bit to one, activates the Timer/Counter Synchronization mode. In this mode, the value that is ...

  • Page 162

    SPI – Serial Peripheral Interface 17.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • ...

  • Page 163

    Figure 17-1. SPI Block Diagram Note: The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low ...

  • Page 164

    Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. ...

  • Page 165

    Assembly Code Example SPI_MasterInit: SPI_MasterTransmit: Wait_Transmit: C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 8272A–AVR–01/10 (1) ; Set MOSI and SCK output, all others input r17,(1<<DD_MOSI)|(1<<DD_SCK) ldi out DDR_SPI,r17 ; Enable SPI, Master, set ...

  • Page 166

    The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 8272A–AVR–01/10 (1) ...

  • Page 167

    SS Pin Functionality 17.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured ...

  • Page 168

    Table 17-2. SPI Mode Figure 17-3. SPI Transfer Format with CPHA = 0 Figure 17-4. SPI Transfer Format with CPHA = 1 8272A–AVR–01/10 SPI Modes Conditions 0 CPOL=0, CPHA=0 1 CPOL=0, CPHA=1 2 CPOL=1, CPHA=0 3 CPOL=1, CPHA=1 SCK ...

  • Page 169

    Register Description 17.5.1 SPCR – SPI Control Register Bit 0x2C (0x4C) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register ...

  • Page 170

    Bits 1:0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between ...

  • Page 171

    SPDR – SPI Data Register Bit 0x2E (0x4E) Read/Write Initial Value The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data ...

  • Page 172

    USART 18.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, ...

  • Page 173

    Figure 18-1. USART Block Diagram Note: The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock ...

  • Page 174

    UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only active when using ...

  • Page 175

    Table 18-1. Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode f OSC UBRRn Some examples of UBRRn values for some system clock frequencies are found in page 195. 18.4.2 ...

  • Page 176

    CPU clock period delay and therefore the maximum external XCKn clock frequency is limited by the following equation: Note that f add some margin to avoid possible loss of data due to frequency variations. 18.4.4 Synchronous ...

  • Page 177

    Figure 18-4. Frame Formats St ( IDLE The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that ...

  • Page 178

    Note that the TXCn Flag must be cleared before each transmission (before UDRn is written used for this purpose. The following simple USART initialization code ...

  • Page 179

    Sending Frames with Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDRn I/O location. ...

  • Page 180

    Assembly Code Example USART_Transmit: C Code Example void USART_Transmit( unsigned int data ) { } Notes: The ninth bit can be used for indicating an address frame when using multi processor communi- cation mode or for other protocol handling ...

  • Page 181

    Data Register Empty interrupt routine must either write new data to UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. ...

  • Page 182

    Assembly Code Example USART_Receive: C Code Example unsigned char USART_Receive( void ) { } Note: The function simply waits for data to be present in the receive buffer by checking the RXCn Flag, before reading the buffer and returning ...

  • Page 183

    Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal ...

  • Page 184

    Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when ...

  • Page 185

    The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. The UPEn bit is set if the next character that can be ...

  • Page 186

    Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (i.e., no communication activity). Figure 18-5. Start Bit Sampling Sample (U2X = 0) ...

  • Page 187

    Figure 18-7. Stop Bit Sampling and Next Start Bit Sampling The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic ...

  • Page 188

    Table 18-2. # (Data+Parity Bit) Table 18-3. # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two ...

  • Page 189

    When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs ...

  • Page 190

    Register Description 18.11.1 UDRn – USART I/O Data Register n Bit Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or ...

  • Page 191

    Data Register Empty interrupt (see description of the UDRIEn bit).UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FEn: Frame Error This bit is set if the next character in the ...

  • Page 192

    Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to ...

  • Page 193

    Bits 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver ...

  • Page 194

    Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, ...

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    Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asyn- chronous operation can be generated by using the UBRR settings in UBRR values which yield an actual baud rate ...

  • Page 196

    Table 18-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 ...

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    Table 18-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 ...

  • Page 198

    Table 18-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 ...

  • Page 199

    USART in SPI Mode 19.1 Features • Full Duplex, Three-wire Synchronous Data Transfer • Master Operation • Supports all four SPI Modes of Operation (Mode and 3) • LSB First or MSB First Data Transfer ...

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    BAUD f OSC UBRRn 19.4 SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams ...