ATMEGA1284P-PU Atmel, ATMEGA1284P-PU Datasheet
ATMEGA1284P-PU
Specifications of ATMEGA1284P-PU
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ATMEGA1284P-PU Summary of contents
Page 1
... Extended Standby • I/O and Packages – 32 Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF • Operating Voltages – 1.8 - 5.5V for ATmega1284P • Speed Grades – MHz @ 1.8 - 5.5V – MHz @ 2.7 - 5.5V – MHz @ 4.5 - 5.5V • ...
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... Pin Configurations Figure 1-1. Note: ATmega1284P 2 Pinout ATmega1284P (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/ICP3/MOSI) PB5 (PCINT14/OC3A/MISO) PB6 (PCINT15/OC3B/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0/T3) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 (PCINT27/TXD1/INT1) PD3 (PCINT28/XCK1/OC1B) PD4 (PCINT29/OC1A) PD5 ...
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... Overview The ATmega1284P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega1284P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...
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... As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega1284P as listed on page 79. ...
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... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega1284P as listed on page 81. ...
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... Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. ATmega1284P 6 8059DS–AVR–11/09 ...
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... USART1 Baud Rate Register Low Byte - - - UMSEL10 UPM11 UPM10 USBS1 TXCIE1 UDRIE1 RXEN1 TXEN1 TXC1 UDRE1 FE1 DOR1 - - - USART0 I/O Data Register - - - USART0 Baud Rate Register Low Byte - - - UMSEL00 UPM01 UPM00 USBS0 TXCIE0 UDRIE0 RXEN0 TXEN0 ATmega1284P Bit 2 Bit 1 Bit ...
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... OCR1AH (0x88) OCR1AL (0x87) ICR1H (0x86) ICR1L (0x85) TCNT1H (0x84) TCNT1L (0x83) Reserved - (0x82) TCCR1C FOC1A (0x81) TCCR1B ICNC1 (0x80) TCCR1A COM1A1 (0x7F) DIDR1 - ATmega1284P 8 Bit 6 Bit 5 Bit 4 Bit 3 TXC0 UDRE0 FE0 DOR0 - - - - - - - - TWAM5 TWAM4 TWAM3 TWAM2 TWEA TWSTA TWSTO TWWC ...
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... Timer/Counter0 Output Compare Register A Timer/Counter0 (8 Bit) FOC0B - - WGM02 COM0A0 COM0B1 COM0B0 - - - - - - EEPROM Address Register Low Byte EEPROM Data Register - EEPM1 EEPM0 EERIE General Purpose I/O Register ATmega1284P Bit 2 Bit 1 Bit 0 ADC2D ADC1D ADC0D - - - - MUX2 MUX1 MUX0 - ADTS2 ADTS1 ADTS0 ADPS2 ADPS1 ADPS0 - - - - ...
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... When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis- ters as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega1284P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions ...
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... PC ← then PC ← then PC ← then PC ← then PC ← then PC ← ⊕ then PC ← ⊕ then PC ← then PC ← then PC ← then PC ← then PC ← then PC ← ATmega1284P Operation Flags #Clocks Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V ...
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... Load Program Memory and Post-Inc ELPM Extended Load Program Memory ELPM Rd, Z Extended Load Program Memory ELPM Rd, Z+ Extended Load Program Memory ATmega1284P 12 Description then PC ← then PC ← then PC ← I/O(P,b) ← 1 I/O(P,b) ← 0 Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← Rd(n+1), Rd(7) ← 0 Rd(0)← ...
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... BREAK Break 8059DS–AVR–11/09 Description (Z) ← R1:R0 Rd ← ← Rr STACK ← ← STACK (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only ATmega1284P Operation Flags #Clocks None None None None None None None None ...
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... Wide, Plastic Dual Inline Package (PDIP) 44M1 44-pad 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) ATmega1284P 14 Ordering Code Package (2) ATmega1284P- AU 44A (2) ATmega1284P- PU 40P6 (2) ATmega1284P- MU 44M1 326. Package Type (1) Operational Range Industrial 8059DS–AVR–11/09 ...
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... Orchard Parkway San Jose, CA 95131 R 8059DS–AVR–11/09 B PIN 1 IDENTIFIER TITLE 44A, 44-lead Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATmega1284P A2 A COMMON DIMENSIONS (Unit of Measure = mm) MIN SYMBOL NOM A – – A1 0.05 – ...
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... A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R ATmega1284P 16 D PIN 0º ~ 15º REF eB TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual ...
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... Pin #1 Chamfer (C 0.30) Option C Pin #1 Notch e (0.20 R) TITLE 44M1, 44-pad 1.0 mm Body, Lead Pitch 0.50 mm, 5.20 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) ATmega1284P SEATING PLANE SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM A ...
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... Errata 8.1 ATmega1284P Rev known Errata. ATmega1284P 18 8059DS–AVR–11/09 ...
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... Removed Note 3 from Table 8-1 on page Updated Assembly Code Example in Updated ”ADC Characteristics” on page Added ”Typical Characteristics” on page Updated figure ”Speed Grades” on page Updated ”Ordering Information” on page Initial revision. ATmega1284P 40. ”Watchdog Timer” on page 53. 332. 335. 326. 343. 19 ...
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