ATMEGA1284P-PU Atmel, ATMEGA1284P-PU Datasheet - Page 161

• Manufacturer Part Number: ATMEGA1284P-PU
• Description: MCU AVR 128K ISP FLASH 40-PDIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1284P-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.11.9
8272A–AVR–01/10
GTCCR – General Timer/Counter Control Register
Bit
0x23 (0x43)
Read/Write
Initial Value
• Bit 7 - TSM: Timer/Counter Synchronization mode
Writing the TSM bit to one, activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSRASY and PSRSYNC bits is kept, hence keepeing the correspond-
ing prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are
halted and can be configured to the same value without the risk of one of them advancing during
configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared
by hardware, and the Timer/Counters start counting simultaneously.
• Bit 1 – PSRASY: Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared
immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous
mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by
hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Syn-
chronization Mode” on page 136 for a description of the Timer/Counter Synchronization mode.
• Bit 0 - PSRSYNC: Prescaler Reset
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor-
mally cleared immediately by hardware, except ifthe TSM bit is set. Note that Timer/Counter1
and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both
timers.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
TSM
R/W
7
0
6
–
R
0
R
5
–
0
R
4
–
0
R
3
–
0
R
2
–
0
PSRASY
R/W
1
0
PSRSYNC
R/W
0
0
GTCCR
161