DSPIC33FJ128GP708-I/PT Microchip Technology, DSPIC33FJ128GP708-I/PT Datasheet - Page 10

• Manufacturer Part Number: DSPIC33FJ128GP708-I/PT
• Description: IC DSPIC MCU/DSP 128K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP708-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 80-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 69
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 69
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164328 - MODULE SKT FOR 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6. Module: Output Compare
7. Module: SPI
DS80446D-page 10
The output compare module will miss a compare
event when the current duty cycle register
(OCxRS) value is 0x0000 (0% duty cycle) and the
OCxRS register is updated with a value of 0x0001.
The compare event is only missed the first time a
value of 0x0001 is written to OCxRS and the PWM
output remains low for one PWM period.
Subsequent PWM high and low times occur as
expected.
Work around
None. If the current OCxRS register value is
0x0000, avoid writing a value of 0x0001 to
OCxRS. Instead, write a value of 0x0002;
however, in this case the duty cycle will be slightly
different from the desired value.
Affected Silicon Revisions
The SPI module will fail to generate frame
synchronization pulses when configured in the
Frame Master mode if the start of data is selected
to
synchronization pulse (FRMEN = 1, SPIFSD = 0,
FRMDLY = 1). Synchronization pulses also will not
be generated if FRMDLY = 0 and SMP = 0.
However, the module functions correctly in Frame
Slave mode, and also when FRMDLY = 0 and
SMP = 1.
Work around
If DMA is not being used, manually drive the SSx
pin (x = 1 or 2) high using the associated PORT
register, and then drive it low after the required
1 bit-time pulse-width. This operation needs to be
performed when the transmit buffer is written.
If DMA is being used, and if no other peripheral
modules are using DMA transfers, use a Timer
interrupt to periodically generate the frame
synchronization
described above) after every 8- or 16-bit period
(depending on the data word size, which is
configured using the MODE 16-bit).
Affected Silicon Revisions
A2
A2
X
X
coincide
A3
A3
X
X
A4
A4
X
X
with
pulse
the
(using
start
of
the
the
method
frame
8. Module: SPI
The SPI module slave select functionality (enabled
by setting SSEN = 1) will not function correctly.
Whether the SSx pin (x = 1 or 2) is high or low, the
SPI data transfer will be completed and an
interrupt will be generated.
Work around
If DMA is not being used, poll the SSx pin state
using the Change Notification (CN) pin associated
to the SSx pin as follows:
1. Disable the SPIx module by clearing the
2. Clear the SSEN bit in the SPIxCON1 register
3. Ensure that the CNx pin is configured as a
4. Enable interrupts for the selected CNx pin by
5. Turn on the weak pull-up device for the
6. Clear the CNIF interrupt flag in the IFSx
7. Select the desired interrupt priority for CNx
8. Enable CNx interrupts using the CNIE control
9. In the CNx Interrupt Service Routine, read the
If DMA is being used, no work around exists.
Affected Silicon Revisions
A2
X
SPIEN bit in the SPIxSTAT register.
to allow the I/O port to control the SSx pin.
digital input by setting the associated bit in the
TRISx register.
setting the appropriate bits in the CNEN1 and
CNEN2 registers.
selected CNx pins by setting the appropriate
bits in the CNPU1 and CNPU2 registers.
register.
interrupts using the CNIP<2:0> control bits in
the IPCx register.
bit in the IECx register.
PORTx register associated to the SSx pin:
a) if the PORTx bit is ‘0’ – enable the SPIx
b) if the PORTx bit is ‘1’ – disable the SPIx
module by setting the SPIEN bit, and
perform the required data read/write.
module by setting the SPIEN bit, clear the
SPI interrupt flag (SPIxIF), perform a
dummy read of the SPIxBUF register,
and return from the Interrupt Service
Routine (ISR).
A3
X
A4
X
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