DSPIC33FJ128GP708-I/PT Microchip Technology, DSPIC33FJ128GP708-I/PT Datasheet - Page 4

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DSPIC33FJ128GP708-I/PT

Manufacturer Part Number
DSPIC33FJ128GP708-I/PT
Description
IC DSPIC MCU/DSP 128K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP708-I/PT

Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
80-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
69
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
69
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164328 - MODULE SKT FOR 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ128GP708-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC33FJ128GP708-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
TABLE 2:
DS80446D-page 4
Operations
Note 1:
Regulator
Oscillator
Module
Internal
Voltage
UART
UART
UART
UART
UART
DMA
DMA
DMA
CPU
PSV
SPI
I
I
I
I
I
2
2
2
2
2
C
C
C
C
C
Only those issues indicated in the last column apply to the current silicon revision.
Functionality
FRC Tuning
High-Speed
Write Mode
Write Mode
SFR Writes
NULL Data
Error Traps
NULL Data
Addressing
Addressing
Addressing
I
SCKx Pins
Auto-Baud
Instruction
PD
Interrupts
IR Mode
IR Mode
Feature
REPEAT
SILICON ISSUE SUMMARY (CONTINUED)
I/O Port
Mode
10-bit
Mode
10-bit
Mode
10-bit
Mode
Current
Number
Item
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
53.
52.
When the UART is in 4x mode (BRGH = 1) and using two Stop
bits (STSEL = 1), it may sample the first Stop bit instead of the
second one.
When an auto-baud is detected, the receive interrupt may
occur twice.
NULL Data Peripheral Write mode for the DMA channel does
not function.
DMA request Fault condition does not generate a DMA error
trap.
DMA channel writes an additional NULL value to the
peripheral register.
Any instruction executed inside a REPEAT loop that produces
a Read-After-Write stall condition, results in the instruction
being executed fewer times than was intended.
For certain values of the TUN<5:0> bits (OSCTUN<5:0>), the
resultant frequencies are incorrect.
The 16x baud clock signal on the BCLK pin is present only
when the module is transmitting.
The SPIxCON1 DISSCK bit does not influence port
functionality.
The BCL bit in I2CSTAT can be cleared only with 16-bit
operation and can be corrupted with 1-bit or 8-bit operations
on I2CSTAT.
When the I
the same address bits (A10 and A9) as other I
A10 and A9 bits may not work as expected.
When the I
address of 0x102, the I2CxRCV register content for the lower
address byte is 0x01 rather than 0x02.
With the I
Interrupt Input functions (if any) associated with SCL and SDA
pins will not reflect the actual digital logic levels on the pins.
The 10-bit slave does not set the RBF flag or load the
I2CxRCV register on address match if the Least Significant
bits (LSbs) of the address are the same as the 7-bit reserved
addresses.
When the VREGS bit (RCON<8>) is set to a logic ‘0’, the
device may reset and higher sleep current may be observed.
An address error trap occurs in certain addressing modes
when accessing the first four bytes of any PSV page.
The UART error interrupt may not occur, or may occur at an
incorrect time, if multiple errors occur during a short period of
time.
When the UART module is operating in 8-bit mode (PDSEL = 0x)
and using the IrDA
incorrectly transmits a data payload of 80h as 00h.
2
C module enabled, the PORT bits and external
2
2
C module is configured for 10-bit addressing using
C module is configured as a 10-bit slave with an
®
encoder/decoder (IREN = 1), the module
Issue Summary
2
© 2010 Microchip Technology Inc.
C devices, the
Revisions
A2 A3 A4
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Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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(1)

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