DSPIC33FJ128GP710A-I/PF Microchip Technology, DSPIC33FJ128GP710A-I/PF Datasheet - Page 229

IC DSPIC MCU/DSP 128K 100-TQFP

DSPIC33FJ128GP710A-I/PF

Manufacturer Part Number
DSPIC33FJ128GP710A-I/PF
Description
IC DSPIC MCU/DSP 128K 100-TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ128GP710A-I/PF

Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
100-TQFP, 100-VQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ128GP710A-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
REGISTER 20-1:
 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4-2
bit 1-0
DCIEN
R/W-0
R/W-0
UNFM
DCIEN: DCI Module Enable bit
1 = Module is enabled
0 = Module is disabled
Unimplemented: Read as ‘0’
DCISIDL: DCI Stop in Idle Control bit
1 = Module will halt in CPU Idle mode
0 = Module will continue to operate in CPU Idle mode
Unimplemented: Read as ‘0’
DLOOP: Digital Loopback Mode Control bit
1 = Digital Loopback mode is enabled. CSDI and CSDO pins internally connected
0 = Digital Loopback mode is disabled
CSCKD: Sample Clock Direction Control bit
1 = CSCK pin is an input when DCI module is enabled
0 = CSCK pin is an output when DCI module is enabled
CSCKE: Sample Clock Edge Control bit
1 = Data changes on serial clock falling edge, sampled on serial clock rising edge
0 = Data changes on serial clock rising edge, sampled on serial clock falling edge
COFSD: Frame Synchronization Direction Control bit
1 = COFS pin is an input when DCI module is enabled
0 = COFS pin is an output when DCI module is enabled
UNFM: Underflow Mode bit
1 = Transmit last value written to the transmit registers on a transmit underflow
0 = Transmit ‘0’s on a transmit underflow
CSDOM: Serial Data Output Mode bit
1 = CSDO pin will be tri-stated during disabled transmit time slots
0 = CSDO pin drives ‘0’s during disabled transmit time slots
DJST: DCI Data Justification Control bit
1 = Data transmission/reception is begun during the same serial clock cycle as the frame
0 = Data transmission/reception is begun one serial clock cycle after frame synchronization pulse
Unimplemented: Read as ‘0’
COFSM<1:0>: Frame Sync Mode bits
11 = 20-bit AC-Link mode
10 = 16-bit AC-Link mode
01 = I
00 = Multi-Channel Frame Sync mode
CSDOM
R/W-0
synchronization pulse
U-0
2
DCICON1: DCI CONTROL REGISTER 1
S Frame Sync mode
dsPIC33FJXXXGPX06A/X08A/X10A
W = Writable bit
‘1’ = Bit is set
DCISIDL
R/W-0
R/W-0
DJST
U-0
U-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
DLOOP
R/W-0
U-0
CSCKD
R/W-0
U-0
x = Bit is unknown
CSCKE
R/W-0
R/W-0
COFSM<1:0>
DS70593B-page 229
COFSD
R/W-0
R/W-0
bit 8
bit 0

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