DSPIC30F5013-20I/PT Microchip Technology, DSPIC30F5013-20I/PT Datasheet
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... Microchip Technology Inc. dsPIC30F5011/5013 High-Performance, 16-bit Digital Signal Controllers Data Sheet DS70116J ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... All DSP instructions are single cycle - Multiply-Accumulate (MAC) operation • Single cycle ±16 shift © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Peripheral Features: • High-current sink/source I/O pins: 25 mA/25 mA • Five 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules • ...
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... Wide operating voltage range (2.5V to 5.5V) • Industrial and Extended temperature ranges • Low power consumption TABLE 1: dsPIC30F5011/5013 CONTROLLER FAMILY Program Memory Device Pins Bytes Instructions dsPIC30F5011 64 66K 22K dsPIC30F5013 80 66K 22K DS70116J-page 4 Output SRAM EEPROM Timer Input Comp/Std Bytes Bytes ...
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... TQFP COFS/RG15 1 T2CK/RC1 2 T3CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF © 2011 Microchip Technology Inc. dsPIC30F5011/5013 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/INT2/RD9 42 IC1/INT1/RD8 dsPIC30F5011 40 OSC2/CLKO/RC15 39 OSC1/CLKI SCL/RG2 36 SDA/RG3 35 EMUC3/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 EMUD3/U1TX/SDO1/RF3 DS70116J-page 5 ...
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... T5CK/RC4 5 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 INT1/RA12 13 INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 DS70116J-page dsPIC30F5013 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI V DD SCL/RG2 SDA/RG3 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8 U1RX/RF2 U1TX/RF3 © 2011 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com © 2011 Microchip Technology Inc. dsPIC30F5011/5013 to receive the most current information on all of our products. DS70116J-page 7 ...
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... NOTES: DS70116J-page 8 © 2011 Microchip Technology Inc. ...
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... Digital Signal Controller (DSC) devices. The dsPIC30F5011/5013 devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture. Figure 1-1 and Figure 1-2 block diagrams for dsPIC30F5011 and dsPIC30F5013, respectively. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Manual” show device DS70116J-page 9 ...
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... OSC2/CLKO/RC15 PORTC EMUC2/OC1/RD0 EMUD2/OC2/RD1 OC3/RD2 OC4/RD3 OC5/IC5/CN13/RD4 OC6/IC6/CN14/RD5 OC7/CN15/RD6 OC8/CN16/RD7 IC1/INT1/RD8 IC2/INT2/RD9 IC3/INT3/RD10 IC4/INT4/RD11 PORTD C1RX/RF0 C1TX/RF1 U1RX/SDI1/RF2 EMUD3/U1TX/SDO1/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 EMUC3/SCK1/INT0/RF6 PORTF C2RX/RG0 C2TX/RG1 SCL/RG2 SDA/RG3 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SS2/CN11/RG9 CSDI/RG12 CSDO/RG13 CSCK/RG14 COFS/RG15 PORTG © 2011 Microchip Technology Inc. ...
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... FIGURE 1-2: dsPIC30F5013 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU Program Counter Stack Address Latch Control Logic Program Memory (66 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch 24 16 Instruction Decode & Control ...
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... Master Clear (Reset) input or programming voltage input. This pin is an active low Reset to the device. Compare Fault A input (for Compare channels and 4). Compare Fault B input (for Compare channels and 8). Compare outputs 1 through 8. Analog = Analog input O = Output P = Power © 2011 Microchip Technology Inc. ...
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... REF Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Description Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. ...
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... NOTES: DS70116J-page 14 © 2011 Microchip Technology Inc. ...
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... Each data word consists of 2 bytes, and most instructions can address data either as words or bytes. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 There are two methods of accessing data stored in program memory: • The upper 32 Kbytes of data space memory can ...
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... DSP Adder/Subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) Status bit. 2.2.3 PROGRAM COUNTER The program counter is 23 bits wide; bit 0 is always clear. Therefore, the PC can address instruction words. DSC devices contain a software stack. for SR layout. © 2011 Microchip Technology Inc. ...
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... DSP AccA Accumulators AccB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2011 Microchip Technology Inc. dsPIC30F5011/5013 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 ...
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... A block diagram of the DSP engine is shown in Figure 2-2. TABLE 2-1: DSP INSTRUCTION SUMMARY Algebraic Instruction Operation CLR – – y) EDAC MAC MAC No change in A MOVSAC MPY – MPY.N MSC – Function © 2011 Microchip Technology Inc. operations, 3-3. ACC WB? Yes No No Yes No Yes No No Yes ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2011 Microchip Technology Inc. dsPIC30F5011/5013 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill DS70116J-page 19 ...
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... OVBTE) in the INTCON1 register (refer to rupts”) is set. This allows the user to take immediate action, for example, to correct system gain. Section 4.0 “Inter- © 2011 Microchip Technology Inc. ...
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... If the COVTE bit in the INTCON1 register is set, a catastrophic over- flow can initiate a trap exception. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 2.4.2.2 Accumulator ‘Write Back’ The MAC class of instructions (with the exception of MPY, MPY ...
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... The barrel shifter is 40-bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is pre- sented to the barrel shifter between bit positions for right shifts, and bit positions for left shifts. © 2011 Microchip Technology Inc. ...
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... In Table 3-1, Program Space Address Construction, bit 23 allows access to the Device ID, the User ID and the Configuration bits. Otherwise, bit 23 is always clear. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 FIGURE 3-1: Reset - GOTO Instruction Reset - Target Address Interrupt Vector Table Manual” ...
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... Program space visibility cannot be used to access bits <23:16> word in program memory. DS70116J-page 24 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> PSVPAG<7:0> bits Program Counter Select 1 EA PSVPAG Reg 8 bits 15 bits EA TBLPAG Reg 8 bits 16 bits 24-bit EA <15> <14:1> <0> PC<22:1> 0 Data EA<15:0> Data EA<15:0> Data EA<14:0> 0 Byte Select © 2011 Microchip Technology Inc. ...
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... Program Memory ‘Phantom’ Byte (read as ‘0’) © 2011 Microchip Technology Inc. dsPIC30F5011/5013 A set of table instructions are provided to move byte or word sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the lsw of the program address; ...
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... Execution in the last iteration - Execution prior to exiting the loop due to an interrupt - Execution upon re-entering the loop after an interrupt is serviced • Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle © 2011 Microchip Technology Inc. ...
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... Access program memory location ; using a data space access Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines the page in program space to which the upper half of data space is being mapped). © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Program Space 0x0000 (1) ...
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... The X data space is used by all instructions and supports all addressing modes, as shown in LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x0FFE 0x1000 Y Data RAM (Y) 0x17FE 0x1800 0x1FFE 0x8000 X Data Unimplemented (X) 0xFFFE Figure 3-6. Figure 3-7. 8 Kbyte Near Data Space © 2011 Microchip Technology Inc. ...
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... FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2011 Microchip Technology Inc. dsPIC30F5011/5013 SFR SPACE UNUSED Y SPACE UNUSED UNUSED MAC Class Ops (Read) ...
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... FIGURE 3-8: MSB 15 0001 Byte1 0x0000 Byte3 0003 0x0000 Byte5 0005 0x0000 ® DATA ALIGNMENT LSB 0000 Byte 0 Byte 2 0002 Byte 4 0004 © 2011 Microchip Technology Inc. ...
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... Note push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> ...
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... DS70116J-page 32 © 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F5011/5013 DS70116J-page 33 ...
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... NOTES: DS70116J-page 34 © 2011 Microchip Technology Inc. ...
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... The INTCON2 register controls the external interrupt request signal behavior and the use of the alternate vector table. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 • INTTREG<15:0> The associated interrupt vector number and the new CPU interrupt priority level are latched into vector number (VECNUM< ...
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... OC8 – Output Compare INT3 – External Interrupt INT4 – External Interrupt – Combined IRQ for CAN2 39-40 47-48 Reserved 41 49 DCI – Codec Transfer Done 42 50 LVD – Low-Voltage Detect 43-53 51-61 Reserved Lowest Natural Order Priority © 2011 Microchip Technology Inc. ...
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... A momentary dip in the power supply to the device has been detected which may result in malfunction. • Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 4.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere ...
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... Address Error Trap Vector Math Error Trap Vector Reserved Vector AIVT Reserved Vector Reserved Vector Interrupt 0 Vector Interrupt 1 Vector — — — Interrupt 52 Vector Interrupt 53 Vector © 2011 Microchip Technology Inc. 0x000000 0x000002 0x000004 0x000014 0x00007E 0x000080 0x000082 0x000084 0x000094 0x0000FE ...
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... The RETFIE (return from interrupt) instruction will unstack the program counter and STATUS registers to return the processor to its state prior to the interrupt sequence. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 4.5 Alternate Vector Table In program memory, the Interrupt Vector Table (IVT) is ...
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... DS70116J-page 40 © 2011 Microchip Technology Inc. ...
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... Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2011 Microchip Technology Inc. dsPIC30F5011/5013 5.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... The only exception to the usage restrictions is for buf- fers that have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a Bidirectional mode (i.e., address boundary checks are performed on both the lower and upper address boundaries). © 2011 Microchip Technology Inc. Stack Pointer, ...
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... MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2011 Microchip Technology Inc. dsPIC30F5011/5013 5.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control reg- registers: ister MODCON<15:0> contains enable flags as well register field to specify the W address registers ...
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... W register that has been designated as the bit-reversed pointer. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer N bytes, addressing and bit-reversed should not be enabled © 2011 Microchip Technology Inc. ...
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... TABLE 5-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address TABLE 5-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 2048 1024 512 256 128 © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Bit-Reversed Address Decimal XB<14:0> Bit-Reversed Address Modifier Value A0 Decimal 0x0400 ...
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... NOTES: DS70116J-page 46 © 2011 Microchip Technology Inc. ...
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... Using NVMADR Addressing Using Table Instruction User/Configuration Space Select © 2011 Microchip Technology Inc. dsPIC30F5011/5013 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... NVMKEY register. Refer to DD “Programming Operations” Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. © 2011 Microchip Technology Inc. Section 6.6 for further details. ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2011 Microchip Technology Inc. dsPIC30F5011/5013 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, program Flash, program, and set WREN bit ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted © 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F5011/5013 DS70116J-page 51 ...
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... NOTES: DS70116J-page 52 © 2011 Microchip Technology Inc. ...
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... The write typ- ically requires complete but the write time will vary with voltage and temperature. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 A program or erase operation on the data EEPROM does not stop the instruction flow. The user is respon- ...
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... Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence © 2011 Microchip Technology Inc. ...
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... NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2011 Microchip Technology Inc. dsPIC30F5011/5013 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared, and the Power-up Timer prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch or software malfunction. © 2011 Microchip Technology Inc. ...
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... WR TRIS WR LAT + WR Port Read LAT Read Port © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Any bit and its associated data and control registers that are not valid for a particular device will be dis- abled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. ...
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... NOP will be OL EXAMPLE 8-1: MOV 0xFF00, W0 MOV W0, TRISB NOP btss PORTB, #13 I/O Cell I/O Pad Input Data PORT WRITE/READ EXAMPLE ; Configure PORTB<15:8> inputs ; and PORTB<7:0> as outputs ; additional instruction cycle ; bit test RB13 and skip if set © 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F5011/5013 DS70116J-page 59 ...
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... DS70116J-page 60 © 2011 Microchip Technology Inc. ...
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... Legend: — = unimplemented, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 8-13: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F5013 (BITS 7-0) SFR Addr. Bit 7 Bit 6 Name CNEN1 00C0 CN7IE ...
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... Event Flag 1 TGATE SOSCO/ T1CK LPOSCEN SOSCI © 2011 Microchip Technology Inc. dsPIC30F5011/5013 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...
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... The respective Timer interrupt flag, T1IF, is located in the IFS0 Status register in the interrupt controller. Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T1IE. The timer interrupt enable bit is located in the IEC0 Control register in the interrupt controller. SOSCI dsPIC30FXXXX SOSCO © 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F5011/5013 DS70116J-page 65 ...
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... NOTES: DS70116J-page 66 © 2011 Microchip Technology Inc. ...
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... Interrupt on a 32-bit period register match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 For 32-bit timer/counter operation, Timer2 is the least significant word and Timer3 is the most significant word of the 32-bit timer ...
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... Timer Configuration bit T32 (T2CON<3>) must be set to ‘ bits are respective to the T2CON register. DS70116J-page TMR3 TMR2 MSB LSB Comparator x 32 PR3 PR2 TGATE (T2CON<6> Gate Sync ’ for a 32-bit timer/counter operation. All control Sync TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2011 Microchip Technology Inc. ...
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... Equal Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK © 2011 Microchip Technology Inc. dsPIC30F5011/5013 PR2 Comparator x 16 TMR2 TGATE TON 1 x Gate Sync PR3 Comparator x 16 ...
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... In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T3IE (IEC0<7>). © 2011 Microchip Technology Inc. ...
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... NOTES: DS70116J-page 72 © 2011 Microchip Technology Inc. ...
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... T4CK Note: Timer Configuration bit T32 (T4CON<3>) must be set to ‘ bits are respective to the T4CON register. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 • The Timer4/5 module does not support the ADC event trigger feature • Timer4/5 can not be utilized by other peripheral ...
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... Timer5: 2: TCS = 1 (16-bit counter) 3: TCS = 0, TGATE = 1 (gated time accumulation) DS70116J-page 74 PR4 Comparator x 16 TMR4 TGATE TON 1 x Gate Sync PR5 Comparator x 16 TMR5 TGATE Sync Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2011 Microchip Technology Inc. ...
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... NOTES: DS70116J-page 76 © 2011 Microchip Technology Inc. ...
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... ICBNE, ICOV ICxCON Data Bus Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 12.1 Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • ...
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... IFSx Status register. Enabling an interrupt is accomplished via the respec- tive capture channel interrupt enable (ICxIE) bit. The capture interrupt enable bit is located in the corresponding IEC Control register. © 2011 Microchip Technology Inc. defined as ...
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... NOTES: DS70116J-page 80 © 2011 Microchip Technology Inc. ...
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... TMR2<15:0 TMR3<15:0> Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through N. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 The key operational features of the output compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...
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... Fault condition has occurred. This state will be maintained until both of the following events have occurred: • The external Fault condition has been removed • The PWM mode has been reenabled by writing to the appropriate control bits . © 2011 Microchip Technology Inc. ...
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... PWM OUTPUT TIMING Duty Cycle TMR3 = PR3 T3IF = 1 (Interrupt Flag) OCxR = OCxRS © 2011 Microchip Technology Inc. dsPIC30F5011/5013 When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • TMRx is cleared • The OCx pin is set ...
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... IFS0 Status register and must be cleared in software. The interrupt is enabled via the respective timer interrupt enable bit (T2IE or T3IE) located in the IEC0 Control register. The output compare interrupt flag is never set during the PWM mode of operation. DS70116J-page 84 © 2011 Microchip Technology Inc. ...
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... NOTES: DS70116J-page 86 © 2011 Microchip Technology Inc. ...
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... SPIxSR. The received data is thus placed in SPIxBUF and the transmit data in SPIxSR is ready for the next transfer. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Note: Both the transmit buffer (SPIxTXB) and the receive buffer (SPIxRXB) are mapped to the same register address, SPIxBUF ...
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... Clock Clock Edge Control Select Enable Master Clock SDOx SDIy SDIx SDOy LSb Serial Clock SCKx SCKy Secondary Primary F Prescaler CY Prescaler 1:1 – 1 16, 64 SPI Slave Serial Input Buffer (SPIyBUF) Shift Register (SPIySR) MSb LSb PROCESSOR 2 © 2011 Microchip Technology Inc. ...
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... The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 14.5 SPI Operation During CPU Idle Mode When the device enters Idle mode, all clock sources remain functional. The SPISIDL bit (SPIxSTAT< ...
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... DS70116J-page 90 © 2011 Microchip Technology Inc. ...
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... Thus, the I C module can operate either as a slave master bus. FIGURE 15-1: PROGRAMMER’S MODEL Bit 15 Bit 15 © 2011 Microchip Technology Inc. dsPIC30F5011/5013 15.1.1 VARIOUS I The following types • slave operation with 7-bit addressing 2 • slave operation with 10-bit addressing 2 • ...
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... LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F CY Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read © 2011 Microchip Technology Inc. ...
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... SCL, such that SDA is valid during SCL high. The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 15.3.2 SLAVE RECEPTION If the R_W bit received is a ‘ ...
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... C bus have de-asserted SCL. This ensures that a write to the SCLREL bit will not violate the minimum high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. © 2011 Microchip Technology Inc. 2 CRCV ...
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... Generate a Stop condition on SDA and SCL. 2 • Configure the I C port to receive data • Generate an ACK condition at the end of a received byte of data © 2011 Microchip Technology Inc. dsPIC30F5011/5013 2 15. Master Operation The master device generates all of the serial clock ...
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... C OPERATION DURING CPU IDLE MODE 2 For the I C, the I2CSIDL bit selects if the module will stop on Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle bus © 2011 Microchip Technology Inc. ...
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... NOTES: DS70116J-page 98 © 2011 Microchip Technology Inc. ...
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... Internal Data Bus UTXBRK Data UxTX Parity Note © 2011 Microchip Technology Inc. dsPIC30F5011/5013 16.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, odd or no parity options (for 8-bit data) • One or two Stop bits • ...
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... Receive Buffer Control 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16x Baud Clock from Baud Rate Generator Read Read Write UxMODE UxSTA – Generate Flags – Generate Interrupt – Shift Data Characters Control Signals UxRXIF © 2011 Microchip Technology Inc. ...
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... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). © 2011 Microchip Technology Inc. dsPIC30F5011/5013 16.3 Transmitting Data 16.3.1 ...
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... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. © 2011 Microchip Technology Inc. RXB) ...
Page 103
... FERR bit set. The break character is loaded into the buffer. No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not yet been received. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 16.6 Address Detect Mode Setting the ADDEN bit (UxSTA< ...
Page 104
... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode or whether the module will continue on Idle. If USIDL = 0, the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. © 2011 Microchip Technology Inc. ...
Page 105
... Microchip Technology Inc. dsPIC30F5011/5013 DS70116J-page 105 ...
Page 106
... NOTES: DS70116J-page 106 © 2011 Microchip Technology Inc. ...
Page 107
... Programmable link to Input Capture module (IC2, for both CAN1 and CAN2) for time-stamping and network synchronization • Low-power Sleep and Idle mode © 2011 Microchip Technology Inc. dsPIC30F5011/5013 The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus ...
Page 108
... Acceptance Filter c RXF3 c Acceptance Filter e RXF4 p t Acceptance Filter RXF5 R M Identifier Data Field Receive RERRCNT Error Counter TERRCNT Transmit Err Pas Error Bus Off Counter Protocol Finite State Machine Bit Timing Bit Timing Logic Generator (1) CiRX © 2011 Microchip Technology Inc. ...
Page 109
... Module Disable mode. The I/O pins will revert to normal I/O function when the module is in the Module Disable mode. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2< ...
Page 110
... End-of-Frame (EOF) field. Reading the RXnIF flag will indicate which receive buffer caused the interrupt. • Wake-up Interrupt: The CAN module has woken up from Disable mode or the device has woken up from Sleep mode. © 2011 Microchip Technology Inc. ...
Page 111
... SOF occurs. When TXREQ is set, the TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR (CiTXnCON<4>) flag bits are automatically cleared. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Setting TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority ...
Page 112
... definition, the nominal bit time has a minimum and a maximum the minimum nominal bit time is 1 μsec corresponding to a maximum bit rate of 1 MHz. Phase Phase Segment 1 Segment 2 Sample Point Figure 17-2. . Also, by definition, Q Sync © 2011 Microchip Technology Inc. ...
Page 113
... SEG1PH<2:0> (CiCFG2<5:3>), and Phase2 Seg is initialized by setting SEG2PH<2:0> (CiCFG2<10:8>). The following requirement must be fulfilled while setting the lengths of the phase segments: Prop Seg + Phase1 Seg > = Phase2 Seg © 2011 Microchip Technology Inc. dsPIC30F5011/5013 17.6.5 SAMPLE POINT The sample point is the point of time at which the bus ...
Page 114
... DS70116J-page 114 © 2011 Microchip Technology Inc. ...
Page 115
... Microchip Technology Inc. dsPIC30F5011/5013 DS70116J-page 115 ...
Page 116
... NOTES: DS70116J-page 116 © 2011 Microchip Technology Inc. ...
Page 117
... CSDOM control bit. This allows other devices to place data on the serial bus during transmission periods not used by the DCI module. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 18.2.3 CSDI PIN The serial data input (CSDI) pin is configured as an input only pin when the module is enabled ...
Page 118
... DCI Mode Selection bits Receive Buffer Registers w/Shadow Transmit Buffer Registers w/Shadow DS70116J-page 118 BCG Control bits Sample Rate /4 Generator Frame Synchronization Generator DCI Buffer Control Unit 15 DCI Shift Register SCKD CSCK FSD COFS 0 CSDI CSDO © 2011 Microchip Technology Inc. ...
Page 119
... Note: The COFSG control bits will have no effect in AC-Link mode since the frame length is set to 256 CSCK periods by the protocol. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 18.3.4 FRAME SYNC MODE CONTROL BITS The type of frame sync signal is selected using the ...
Page 120
... LSB S12 S12 S12 Tag Tag Tag bit 2 bit 1 LSb MSb bit 14 bit 13 MSB LSB MSB 2 S protocol does not specify word length – this LSB © 2011 Microchip Technology Inc. ...
Page 121
... When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits have no effect on the operation of the DCI module. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 EQUATION 18-2: The required bit clock frequency will be determined by the system sampling rate and frame size. Typical bit ...
Page 122
... In this case, the buffer control unit counter would be incre- mented twice during a data frame but only one receive register location would be filled with data. © 2011 Microchip Technology Inc. ...
Page 123
... SLOT status bits to determine what data should be loaded into the buffer registers to resynchronize the software with the DCI module. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 18.3.16 TRANSMIT STATUS BITS There are two transmit status bits in the DCISTAT SFR. ...
Page 124
... LSbs of the data word are set to ‘0’ by the module. This truncation of the time slots limits the A/D and DAC data to 16 bits but permits proper data alignment in the TXBUF and RXBUF registers. Each RXBUF and TXBUF register will contain one data time slot value. © 2011 Microchip Technology Inc. ...
Page 125
... TSCON and RSCON SFRs. Since the total available buffer length is 64 bits, it would take 4 consecutive interrupts to transfer the AC-Link frame. The application software must keep track of the current AC-Link frame segment. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 2 18.7 I ...
Page 126
... DS70116J-page 126 © 2011 Microchip Technology Inc. ...
Page 127
... AN13 1110 AN14 1111 AN15 V AN1 © 2011 Microchip Technology Inc. dsPIC30F5011/5013 The ADC module has six 16-bit registers: • ADC Control Register 1 (ADCON1) • ADC Control Register 2 (ADCON2) • ADC Control Register 3 (ADCON3) • ADC Input Select Register (ADCHS) • ADC Port Configuration Register (ADPCFG) • ...
Page 128
... ADCSSL register is ‘1’, the corre- sponding input is selected. The inputs are always scanned from lower to higher numbered inputs, starting after each interrupt. If the number of inputs selected is greater than the number of samples taken per interrupt, the higher numbered inputs are unused. © 2011 Microchip Technology Inc. ...
Page 129
... There are 64 possible options for T EQUATION 19-1: ADC CONVERSION CLOCK (0.5*(ADCS<5:0> © 2011 Microchip Technology Inc. dsPIC30F5011/5013 The internal RC oscillator is selected by setting the ADRC bit. For correct ADC conversions, the ADC conversion clock (T ) must be selected to ensure a minimum T AD time of 334 nsec (for V “ ...
Page 130
... DS70116J-page 130 R Max V Temperature DD s 2.5 kΩ 4.5V to -40°C to +85°C 5.5V 2.5 kΩ 3.0V to -40°C to +125°C 5.5V Channels Configuration REF REF CH X ANx S/H ADC REF REF ANx S/H ADC ANx REF © 2011 Microchip Technology Inc. ...
Page 131
... Figure 19-2 depicts the recommended circuit for the conversion rates above 100 ksps. The dsPIC30F5013 is shown as an example. FIGURE 19-2: ADC VOLTAGE REFERENCE SCHEMATIC 0.1 μF 0.01 μF 10 The configuration procedures below give the required setup values for the conversion speeds above 100 ksps ...
Page 132
... ≤ 250Ω Sampling Switch leakage V = 0.6V T ± 500 nA PIN AD CONV AD . The combined impedance HOLD , is 2.5 kΩ. After the S ≤ 3 kΩ HOLD = DAC capacitance = negligible if Rs ≤ 2.5 kΩ. © 2011 Microchip Technology Inc. ...
Page 133
... If the ADC interrupt is enabled, the device wakes up from Sleep. If the ADC interrupt is not enabled, the ADC module is turned off, although the ADON bit remains set. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 19.10.2 A/D OPERATION DURING CPU IDLE MODE The ADSIDL bit selects if the module stops on Idle or continues on Idle ...
Page 134
... Any external components connected (via high impedance analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin and V as ESD DD SS and the input voltage exceeds this SS © 2011 Microchip Technology Inc. ...
Page 135
... Microchip Technology Inc. dsPIC30F5011/5013 DS70116J-page 135 ...
Page 136
... NOTES: DS70116J-page 136 © 2011 Microchip Technology Inc. ...
Page 137
... In Idle mode, the clock sources are still active but the CPU is shut-off. The RC oscillator option saves system cost while the LP crystal option saves power. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following features: • ...
Page 138
... RC oscillator. Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation MHz. DS70116J-page 138 Description (1) . (2) . (1) . (1) . (1) . (3) /4 output . OSC (3) . © 2011 Microchip Technology Inc. ...
Page 139
... FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 TUN<3:0> 4 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2011 Microchip Technology Inc. dsPIC30F5011/5013 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Clock ...
Page 140
... Returning to the faster main oscillator still requires a start-up time. OSC2 FPR1 FPR0 Function CLKO CLKO OSC2 0 0 OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 OSC2 1 0 — — (Notes 1, 2) (Notes — — (Notes 1, 2) © 2011 Microchip Technology Inc. ...
Page 141
... PLL multiplier (respectively) is applied. Note: When a 16x PLL is used, the FRC fre- quency must not be tuned to a frequency greater than 7.5 MHz. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 TABLE 20-4: TUN<3:0> Bits 0111 ...
Page 142
... To write to the OSCCON high byte, the following instructions must be executed without any other instructions in between: Byte Write 0x78 to OSCCON high Byte Write 0x9A to OSCCON high Byte write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. © 2011 Microchip Technology Inc. ...
Page 143
... V DD Brown-out Reset BOREN Trap Conflict Illegal Opcode/ Uninitialized W Register © 2011 Microchip Technology Inc. dsPIC30F5011/5013 20.3.1 POR: POWER-ON RESET A power-on event will generate an internal POR pulse when a V rise is detected. The Reset pulse will occur DD at the POR circuit threshold voltage (V nominally 1 ...
Page 144
... INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset DS70116J-page 144 T OST T PWRT T OST T PWRT T OST T PWRT ) DD ): CASE CASE 2 DD © 2011 Microchip Technology Inc. ...
Page 145
... Refer to the Electrical Specifications in the specific device data sheet for BOR voltage limit specifications. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source based on the device Configuration bit values (FOS< ...
Page 146
... Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70116J-page 146 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( © 2011 Microchip Technology Inc. ...
Page 147
... In some devices, the LVD threshold voltage may be applied externally on the LVDIN pin. The LVD module is enabled by setting the LVDEN bit (RCON<12>). © 2011 Microchip Technology Inc. dsPIC30F5011/5013 20.6 Power-Saving Modes There are two power-saving states that can be entered through the execution of a special instruction, PWRSAV ...
Page 148
... This device supports an Advanced implementation of CodeGuard™ Security. Please refer to the “CodeGuard Security” chapter (DS70180) for information on how CodeGuard Security may be used in your application. ≥ 4.5V. © 2011 Microchip Technology Inc. ...
Page 149
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of 1 instruction cycle (assuming the module control registers are already configured to enable module operation). © 2011 Microchip Technology Inc. dsPIC30F5011/5013 20.9 In-Circuit Debugger ® When MPLAB ICD 2 is selected as a Debugger, the In-Circuit Debugging functionality is enabled ...
Page 150
... DS70116J-page 150 © 2011 Microchip Technology Inc. ...
Page 151
... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • ...
Page 152
... Moreover, double word moves require two cycles. The double word instructions execute in two instruction cycles. Note: For more details on the instruction set, refer to the “16-bit MCU and DSC Programmer’s Reference (DS70157). Description © 2011 Microchip Technology Inc. Manual” ...
Page 153
... Y data space prefetch address register for DSP instructions ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space prefetch destination register for DSP instructions ∈ {W4..W7} Wyd © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Description DS70116J-page 153 ...
Page 154
... Branch if Accumulator A overflow Branch if Accumulator B overflow Branch if Overflow Branch if Accumulator A saturated Branch if Accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> © 2011 Microchip Technology Inc Status Flags Cycles Affected 1 1 OA,OB,SA, C,DC,N,OV,Z 1 ...
Page 155
... DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2011 Microchip Technology Inc. dsPIC30F5011/5013 # of Description Words Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 156
... Move f to WREG Move 16-bit literal to Wn Move 8-bit literal to Wn Move Move Move WREG to f Move Double from W(ns):W(ns+ Move Double from Ws to W(nd+1):W(nd) Prefetch and store accumulator © 2011 Microchip Technology Inc Status Flags Cycles Affected 1 18 N,Z,C,OV 1 ...
Page 157
... RRC Ws,Wd 66 RRNC RRNC f RRNC f,WREG RRNC Ws,Wd © 2011 Microchip Technology Inc. dsPIC30F5011/5013 # of Description Words Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) ...
Page 158
... Wn = byte swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink frame pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-extend Ws © 2011 Microchip Technology Inc Status Flags Cycles Affected 1 1 None 1 1 None 1 ...
Page 159
... MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits © 2011 Microchip Technology Inc. dsPIC30F5011/5013 22.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...
Page 160
... Support for the entire device instruction set ® standard HEX • Support for fixed-point and floating-point data • Command line interface • Rich directive set • Flexible macro language • MPLAB IDE compatibility © 2011 Microchip Technology Inc. ...
Page 161
... Microchip Technology Inc. dsPIC30F5011/5013 22.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- ...
Page 162
... This usually includes a single application and debug capability, all for DDMAX on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ® © 2011 Microchip Technology Inc. ...
Page 163
... Exposure to maximum rating conditions for extended periods may affect device reliability. Note: All peripheral electrical characteristics are specified. For exact peripherals available on specific devices, please refer to the dsPIC30F5011/5013 Controller Family table. See © 2011 Microchip Technology Inc. dsPIC30F5011/5013 (1) (except V and MCLR) ...
Page 164
... Min Typ Max Unit -40 — +125 °C -40 — +85 °C -40 — +150 °C -40 — +85 °C -40 — +150 °C -40 — +125 ° INT I O θ Typ Max Unit Notes 39 — °C — °C/W 1 © 2011 Microchip Technology Inc. ...
Page 165
... All I/O pins are configured as Inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory DD are operational. No peripheral modules are operating. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 166
... OSC1 DD 4 MIPS 10 MIPS 20 MIPS 30 MIPS . DD © 2011 Microchip Technology Inc. ...
Page 167
... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base I current is measured with core off, clock on and all modules turned off. IDLE © 2011 Microchip Technology Inc. dsPIC30F5011/5013 ) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 168
... PD (3) Base Power Down Current (3) Watchdog Timer Current: ΔI WDT (3) Timer 1 w/32 kHz Crystal: Δ (3) BOR On: ΔI BOR LVD (3) Low-Voltage Detect: ΔI © 2011 Microchip Technology Inc. ...
Page 169
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 5: Negative current is defined as current sourced by the pin. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 170
... Industrial A ≤ +125°C for Extended A Units Conditions 8.5 mA 2.0 mA 1.6 mA 2.0 mA -3.0 mA -2.0 mA -1.3 mA -2.0 mA XTL, XT, HS and LP modes when external clock is used to drive OSC1 Osc mode mode © 2011 Microchip Technology Inc. ...
Page 171
... These parameters are characterized but not tested in manufacturing. 2: These values not in usable operating range. FIGURE 23-2: BROWN-OUT RESET CHARACTERISTICS V DD BO10 (Device in Brown-out Reset) RESET (due to BOR) © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min (2) transition LVDL = 0000 — ...
Page 172
... C ≤ T ≤ +85° Using EECON to read/write V = Minimum operating MIN voltage ms RTSP Provided no other specifications are violated mA Row Erase -40° C ≤ T ≤ +85° Minimum operating MIN voltage RTSP Provided no other specifications are violated mA Row Erase mA Bulk Erase © 2011 Microchip Technology Inc. ...
Page 173
... LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Pin FIGURE 23-4: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature A -40°C ≤ T ...
Page 174
... EC with 8x PLL MHz EC with 16x PLL MHz RC MHz XTL MHz XT MHz XT with 4x PLL MHz XT with 8x PLL MHz XT with 16x PLL MHz HS kHz LP — See parameter OS10 for F value OSC ns See Table 23- See parameter DO31 ns See parameter DO32 ). CY © 2011 Microchip Technology Inc. ...
Page 175
... Operating temperature Param Characteristic No. OS61 x4 PLL x8 PLL x16 PLL Note 1: These parameters are characterized but not tested in manufacturing. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 = 2 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature A -40°C ≤ T ...
Page 176
... Industrial ≤ +125°C for Extended Conditions ≤ +85° 3.0-5. ≤ +125° 3.0-5. ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions V = 5.0V, ±10 3.3V, ±10 2.5V DD © 2011 Microchip Technology Inc. ...
Page 177
... These parameters are asynchronous events not related to any internal clock edges. 2: Measurements are taken in RC mode and EC mode where CLKOUT output These parameters are characterized but not tested in manufacturing. 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 DI35 DI40 New Value DO31 DO32 Standard Operating Conditions: 2 ...
Page 178
... TIMER TIMING CHARACTERISTICS V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal RESET Watchdog Timer RESET I/O Pins SY35 FSCM Delay Note: Refer to Figure 23-3 for load conditions. DS70116J-page 178 SY10 SY20 SY13 SY13 © 2011 Microchip Technology Inc. ...
Page 179
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 3: Refer to Figure 23-2 and Table 23-11 © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) ...
Page 180
... Band Gap Stable ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions Defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable. RCON<13> Status bit © 2011 Microchip Technology Inc. ...
Page 181
... TCS (T1CON, bit 1)) TA20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note: Timer1 is a Type A. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 182
... T — CY ≤ +85°C for Industrial A ≤ +125°C for Extended A Max Units Conditions — ns Must also meet parameter TC15 — ns Must also meet parameter TC15 — prescale value (1, 8, 64, 256) 1.5 — © 2011 Microchip Technology Inc. ...
Page 183
... IC11 TccH ICx Input High Time IC15 TccP ICx Input Period Note 1: These parameters are characterized but not tested in manufacturing. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 IC10 IC11 IC15 for load conditions. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ ...
Page 184
... T Operating temperature -40°C ≤ T (1) (2) Min Typ Max — — — — — — ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions ns See Parameter DO32 ns See Parameter DO31 © 2011 Microchip Technology Inc. ...
Page 185
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...
Page 186
... CS55 CS56 CS35 CS51 CS50 HIGH-Z CSDO CSDI Note: Refer to Figure 23-3 for load conditions. DS70116J-page 186 2 S MODES) TIMING CHARACTERISTICS CS11 CS10 CS21 CS20 MSb CS30 MSb IN CS40 CS41 CS20 CS21 70 LSb HIGH-Z CS31 LSb IN © 2011 Microchip Technology Inc. ...
Page 187
... The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all DCI pins. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 2 S MODES) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 188
... CS20 CS70 CS75 LSb CS75 ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions Bit clock is input ns ns μs Note 1 μs Note 1 μs Note pF LOAD pF LOAD pF LOAD pF LOAD DD ns © 2011 Microchip Technology Inc. ...
Page 189
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 SP10 SP21 SP20 SP21 SP20 ...
Page 190
... Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — ns — ns See Parameter DO32 — ns See Parameter DO31 — ns See Parameter DO32 — ns See Parameter DO31 30 ns — ns — ns — ns © 2011 Microchip Technology Inc. ...
Page 191
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 SP70 SP73 SP72 SP73 ...
Page 192
... SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SP30,SP31 SDI SDI X MSb IN SP41 SP40 Note: Refer to Figure 23-3 for load conditions. DS70116J-page 192 SP70 SP72 SP73 SP35 SP73 SP72 SP52 BIT14 - - - - - -1 LSb BIT14 - - - -1 LSb IN SP52 SP51 © 2011 Microchip Technology Inc. ...
Page 193
... The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) ...
Page 194
... C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 23-3 for load conditions. DS70116J-page 194 IM11 IM10 IM26 IM25 IM40 IM34 IM33 Stop Condition IM21 IM33 IM45 © 2011 Microchip Technology Inc. ...
Page 195
... BRG is the value of the I C Baud Rate Generator. Refer to Section 21. “Inter-Integrated Circuit™ the “dsPIC30F Family Reference Manual” (DS70046). 2: Maximum pin capacitance = 10 pF for all I © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 196
... IS30 SDA Start Condition 2 FIGURE 23-21: I C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 SCL IS30 IS31 SDA In IS40 SDA Out DS70116J-page 196 IS33 IS11 IS10 IS26 IS25 IS40 IS34 Stop Condition IS21 IS33 IS45 © 2011 Microchip Technology Inc. ...
Page 197
... Bus Free Time BF SDA IS50 C Bus Capacitive Loading B Note 1: Maximum pin capacitance = 10 pF for all I © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +125°C for Extended ...
Page 198
... T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A (1) (2) Min Typ Max — — — — — — 500 — — New Value Units Conditions ns See parameter DO32 ns See parameter DO31 ns © 2011 Microchip Technology Inc. ...
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... AD23A G Gain Error ERR Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. © 2011 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40° ...
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... Dynamic Performance — -71 — — 68 — — 83 — — — 100 kHz 10.95 11.1 — ≤ +85°C for Industrial ≤ +125°C for Extended Conditions INL SS REFL 0V REFH INL SS REFL 0V REFH — Guaranteed bits © 2011 Microchip Technology Inc. ...