AT89C51ED2-RDTUM Atmel, AT89C51ED2-RDTUM Datasheet - Page 122

• Manufacturer Part Number: AT89C51ED2-RDTUM
• Description: IC 8051 MCU FLASH 64K 64VQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51ED2-RDTUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Cpu Family: AT89
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Total Internal Ram Size: 2KB
• # I/os (max): 50
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: VQFP
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

25.3.6
25.3.7
122
AT89C51RD2/ED2
External Data Memory Read Cycle
Serial Port Timing - Shift Register Mode
PORT 0
PORT 2
ALE
PSEN
RD
OR SFR-P2
ADDRESS
Table 25-7.
Table 25-8.
Symbol
T
T
T
T
T
QVHX
XHQX
XHDX
XHDV
XLXL
Symbol
Symbol Description
AC Parameters for a Fix Clock
T
T
T
T
T
QVHX
XHQX
XHDX
XHDV
XLXL
A0-A7
T
LLAX
T
AVWL
T
LLWL
Parameter
Serial port clock cycle time
Output data set-up to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
T
AVDV
T
LLDV
ADDRESS A8-A15 OR SFR P2
T
RLAZ
Min
300
200
30
0
T
RLRH
-M
DATA IN
T
T
WHLH
RHDX
T
RHDZ
Max
117
4235K–8051–05/08
Units
ns
ns
ns
ns
ns