DSPIC30F6012A-30I/PT Microchip Technology, DSPIC30F6012A-30I/PT Datasheet - Page 37

• Manufacturer Part Number: DSPIC30F6012A-30I/PT
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012A-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 144KB (48K x 24)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 52
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F6012A30IP

11.4
Programming
Section 11.4.1 “Programming Operations”
Section 11.4.3 “Starting and Stopping a Program-
ming
in
Normal-Voltage Systems”
“Reading the Application ID
operations must use serial execution, as described in
Section 11.2 “ICSP
11.4.1
Flash memory write and erase operations are
controlled by the NVMCON register. Programming is
performed by setting NVMCON to select the type of
erase operation
(Table
programming and initiating the programming by setting
the WR control bit, NVMCON<15>.
In ICSP mode, all programming operations are
externally timed. An external 2 ms delay must be used
between setting the WR control bit and clearing the WR
control bit to complete the programming operation.
TABLE 11-2:
© 2010 Microchip Technology Inc.
0x407F
0x4075
0x4074
0x4072
0x4071
0x406E
0x4066
0x405E
0x4056
0x404E
0x4046
NVMCON
Section 11.5 “Erasing Program Memory in
Value
Cycle”. Step-by-step procedures are described
11-3), writing a key sequence to enable the
Flash Memory Programming in
ICSP Mode
PROGRAMMING OPERATIONS
Erase all code memory, data memory
(does not erase UNIT ID).
Erase 1 row (16 words) of data
EEPROM.
Erase 1 word of data EEPROM.
Erase all executive memory.
Erase 1 row (32 instruction words)
from 1 panel of code memory.
Erase Boot Secure and General
Segments, then erase FBS, FSS and
FGS configuration registers.
Erase all Data EEPROM allocated to
Boot Segment.
Erase Secure and General Segments,
then erase FSS and FGS configuration
registers.
Erase all Data EEPROM allocated to
Secure Segment.
Erase General Segment, then erase
FGS configuration register.
Erase all Data EEPROM allocated to
General Segment.
in
NVMCON ERASE
OPERATIONS
(Table
ICSP
Operation”.
Erase Operation
11-2) or write operation
mode
Word”. All programming
through
is
Section 11.13
described
through
in
TABLE 11-3:
11.4.2
Writes to the WR bit (NVMCON<15>) are locked to
prevent accidental programming from taking place.
Writing a key sequence to the NVMKEY register
unlocks the WR bit and allows it to be written to. The
unlock sequence is performed as follows:
11.4.3
Once the unlock key sequence has been written to the
NVMKEY register, the WR bit (NVMCON<15>) is used
to start and stop an erase or write cycle. Setting the WR
bit initiates the programming cycle. Clearing the WR bit
terminates the programming cycle.
All erase and write cycles must be externally timed. An
external delay must be used between setting and
clearing the WR bit. Starting and stopping a
programming cycle is performed as follows:
11.5
The procedure for erasing program memory (all code
memory, data memory, executive memory and code-
protect bits) consists of setting NVMCON to 0x407F,
unlocking NVMCON for erasing and then executing the
programming cycle. This method of bulk erasing pro-
gram memory only works for systems where V
between 4.5 volts and 5.5 volts. The method for erasing
program memory for systems with a lower V
volts-4.5 volts) is described in
Memory”.
0x4008
0x4005
0x4004
0x4001
NVMCON
Note:
Value
MOV
MOV
MOV
MOV
BSET
<Wait 2 ms>
BCLR
Erasing Program Memory in
Normal-Voltage Systems
UNLOCKING NVMCON FOR
PROGRAMMING
Any working register, or working register
pair, can be used to write the unlock
sequence.
STARTING AND STOPPING A
PROGRAMMING CYCLE
#0x55, W8
W8, NVMKEY
#0xAA, W9
W9, NVMKEY
NVMCON, #WR
NVMCON, #WR
Write 1 word to configuration
memory.
Write 1 row (16 words) to data memory.
Write 1 word to data memory.
Write 1 row (32 instruction words) into
1 panel of program memory.
NVMCON WRITE
OPERATIONS
Write Operation
Section 6.1 “Erasing
DS70102K-page 37
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