AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 333

IC MCU AVR32 128KB FLASH 144LQFP

AT32UC3A0128-ALUT

Manufacturer Part Number
AT32UC3A0128-ALUT
Description
IC MCU AVR32 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets

Specifications of AT32UC3A0128-ALUT

Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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Price
Part Number:
AT32UC3A0128-ALUT
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26.7.8
26.7.8.1
32058J–AVR32–04/11
SPI Mode
Modes of Operation
The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides com-
munication with external devices in Master or Slave Mode. It also enables communication
between processors if an external processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to
other SPIs. During a data transfer, one SPI system acts as the “master” which controls the data
flow, while the other devices act as “slaves'' which have data shifted into and out by the master.
Different CPUs can take turns being masters and one master may simultaneously shift data into
multiple slaves. (Multiple Master Protocol is the opposite of Single Master Protocol, where one
CPU is always the master while all of the others are always slaves.) However, only one slave
may drive its output to write data back to the master at any given time.
A slave device is selected when its NSS signal is asserted by the master. The USART in SPI
Master mode can address only one SPI Slave because it can generate only one NSS signal.
The SPI system consists of two data lines and two control lines:
• Master Out Slave In (MOSI): This data line supplies the output data from the master shifted
• Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of
• Serial Clock (CLK): This control line is driven by the master and regulates the flow of the data
• Slave Select (NSS): This control line allows the master to select or deselect the slave.
The USART can operate in Master Mode or in Slave Mode.
Operation in SPI Master Mode is programmed by writing at 0xE the MODE field in the Mode
Register. In this case the SPI lines must be connected as described below:
• the MOSI line is driven by the output pin TXD
• the MISO line drives the input pin RXD
• the CLK line is driven by the output pin CLK
• the NSS line is driven by the output pin RTS
Operation in SPI Slave Mode is programmed by writing at 0xF the MODE field in the Mode Reg-
ister. In this case the SPI lines must be connected as described below:
• the MOSI line drives the input pin RXD
• the MISO line is driven by the output pin TXD
• the CLK line drives the input pin CLK
• the NSS line drives the input pin CTS
In order to avoid unpredicted behavior, any change of the SPI Mode must be followed by a soft-
ware reset of the transmitter and of the receiver (except the initial configuration after a hardware
reset).
into the input of the slave.
the master.
bits. The master may transmit data at a variety of baud rates. The CLK line cycles once for
each bit that is transmitted.
AT32UC3A
333

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