AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 401

• Manufacturer Part Number: AT32UC3A0128-ALUT
• Description: IC MCU AVR32 128KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A0128-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 109
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, RS-485, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 66MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 27-35. Page Mode Read Protocol (Address MSB and LSB are defined in
27.6.9.2
32058J–AVR32–04/11
A[MSB]
D[15:0]
A[LSB]
CLK_SMC
NRD
NCS
Byte Access Type in Page Mode
The NRD and NCS signals are held low during all read transfers, whatever the programmed val-
ues of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS
timings are identical. The pulse length of the first access to the page is defined with the
NCS_RD_PULSE field of the PULSE register. The pulse length of subsequent accesses within
the page are defined using the NRD_PULSE parameter.
In page mode, the programming of the read timings is described in
Table 27-6.
The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE
timings as page access timing (t
the programmed value for t
The Byte Access Type configuration remains active in page mode. For 16-bit or 32-bit page
mode devices that require byte selection signals, configure the BAT field of the REGISTER to 0
(byte select access type).
Parameter
READ_MODE
NCS_RD_SETUP
NCS_RD_PULSE
NRD_SETUP
NRD_PULSE
NRD_CYCLE
NCS_RD_PULSE
Programming of Read Timings in Page Mode
t
pa
Value
‘x’
‘x’
t
‘x’
t
‘x’
pa
sa
pa
is shorter than the programmed value for t
pa
) and the NRD_PULSE for accesses to the page (t
Definition
No impact
No impact
Access time of first access to the page
No impact
Access time of subsequent accesses in the page
No impact
NRD_PULSE
t
sa
Table
27-5)
NRD_PULSE
t
sa
Table
sa
.
27-6:
AT32UC3A
sa
), even if
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