AT32UC3A0256-ALUT Atmel, AT32UC3A0256-ALUT Datasheet - Page 520

• Manufacturer Part Number: AT32UC3A0256-ALUT
• Description: IC MCU AVR32 256KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A0256-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 109
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, RS-485, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 109
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 144LQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

30.7.2.15
30.7.2.16
30.7.2.17
30.7.2.17.1 Global Interrupts
32058J–AVR32–04/11
CRC Error
Interrupts
Overflow
An underflow can not occur during OUT stage on a CPU action, since the firmware may read
only if the bank is not empty (RXOUTI = 1 or RWALL = 1).
An underflow can also occur during OUT stage if the host sends a packet while the bank is
already full. Typically, the CPU is not fast enough. The packet is lost.
An underflow can not occur during IN stage on a CPU action, since the firmware may write only
if the bank is not full (TXINI = 1 or RWALL = 1).
This error exists for all endpoint types. It raises the Overflow interrupt (OVERFI), what triggers
an EPXINT interrupt if OVERFE = 1.
An overflow can occur during OUT stage if the host attempts to write into a bank that is too small
for the packet. The packet is acknowledged and the Received OUT Data interrupt (RXOUTI) is
raised as if no overflow had occurred. The bank is filled with all the first bytes of the packet that
fit in.
An overflow can not occur during IN stage on a CPU action, since the firmware may write only if
the bank is not full (TXINI = 1 or RWALL = 1).
This error exists only for isochronous OUT endpoints. It raises the CRC Error interrupt
(CRCERRI), what triggers an EPXINT interrupt if CRCERRE = 1.
A CRC error can occur during OUT stage if the USB controller detects a corrupted received
packet. The OUT packet is stored in the bank as if no CRC error had occurred (RXOUTI is
raised).
See the structure of the USB device interrupt system on
There are two kinds of device interrupts: processing, i.e. their generation is part of the normal
processing, and exception, i.e. errors (not related to CPU exceptions).
The processing device global interrupts are:
The exception device global interrupts are:
•the Suspend interrupt (SUSP);
•the Start of Frame interrupt (SOF) with no frame number CRC error (FNCERR = 0);
•the End of Reset interrupt (EORST);
•the Wake-Up interrupt (WAKEUP);
•the End of Resume interrupt (EORSM);
•the Upstream Resume interrupt (UPRSM);
•the Endpoint X interrupt (EPXINT);
•the DMA Channel X interrupt (DMAXINT).
•the Start of Frame interrupt (SOF) with a frame number CRC error (FNCERR = 1).
Figure 30-6 on page
AT32UC3A
504.
520