AT32UC3A0256-ALUT Atmel, AT32UC3A0256-ALUT Datasheet - Page 583

IC MCU AVR32 256KB FLASH 144LQFP

AT32UC3A0256-ALUT

Manufacturer Part Number
AT32UC3A0256-ALUT
Description
IC MCU AVR32 256KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets

Specifications of AT32UC3A0256-ALUT

Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
64KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
Package
144LQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A0256-ALUT
Manufacturer:
ATMEL
Quantity:
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Part Number:
AT32UC3A0256-ALUT
Manufacturer:
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Quantity:
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• OVERFE: Overflow Interrupt Enable
Set by software (by setting the OVERFES bit) to enable the Overflow interrupt (OVERFI).
Clear by software (by setting the OVERFEC bit) to disable the Overflow interrupt (OVERFI).
• STALLEDE: STALLed Interrupt Enable
Set by software (by setting the STALLEDES bit) to enable the STALLed interrupt (STALLEDI).
Clear by software (by setting the STALLEDEC bit) to disable the STALLed interrupt (STALLEDI).
• CRCERRE: CRC Error Interrupt Enable
Set by software (by setting the CRCERRES bit) to enable the CRC Error interrupt (CRCERRI).
Clear by software (by setting the CRCERREC bit) to disable the CRC Error interrupt (CRCERRI).
• SHORTPACKETE: Short Packet Interrupt Enable
Set by software (by setting the SHORTPACKETES bit) to enable the Short Packet interrupt (SHORTPACKET).
Clear by software (by setting the SHORTPACKETEC bit) to disable the Short Packet interrupt (SHORTPACKET).
• NBUSYBKE: Number of Busy Banks Interrupt Enable
Set by software (by setting the NBUSYBKES bit) to enable the Number of Busy Banks interrupt (NBUSYBK).
Clear by software (by setting the NBUSYBKEC bit) to disable the Number of Busy Banks interrupt (NBUSYBK).
• KILLBK: Kill IN Bank
Set by software (by setting the KILLBKS bit) to kill the last written bank.
Cleared by hardware when the bank is killed.
Caution: The bank is really cleared when the “kill packet” procedure is accepted by the USB macro core. This bit is auto-
matically cleared after the end of the procedure:
The software shall wait for this bit to be cleared before trying to kill another packet.
Note that this kill request is refused if at the same time an IN token is coming and the last bank is the current one being sent
on the USB line. If at least 2 banks are ready to be sent, there is no problem to kill a packet even if an IN token is coming.
Indeed, in this case, the current bank is sent (IN transfer) while the last bank is killed.
• FIFOCON: FIFO Control
For control endpoints:
For IN endpoints:
For OUT endpoints:
32058J–AVR32–04/11
– The bank is really cleared or the bank is sent (IN transfer): NBUSYBK is decremented.
– The bank is not cleared but sent (IN transfer): NBUSYBK is decremented.
– The bank is not cleared because it was empty.
The FIFOCON and RWALL bits are irrelevant. The software shall therefore never use them on these endpoints.
When read, their value is always 0.
Set by hardware when the current bank is free, at the same time as TXINI.
Clear by software (by setting the FIFOCONC bit) to send the FIFO data and to switch to the next bank.
Set by hardware when the current bank is full, at the same time as RXOUTI.
AT32UC3A
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