AT32UC3A0256-ALUT Atmel, AT32UC3A0256-ALUT Datasheet - Page 753

IC MCU AVR32 256KB FLASH 144LQFP

AT32UC3A0256-ALUT

Manufacturer Part Number
AT32UC3A0256-ALUT
Description
IC MCU AVR32 256KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets

Specifications of AT32UC3A0256-ALUT

Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
64KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
Package
144LQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A0256-ALUT
Manufacturer:
ATMEL
Quantity:
167
Part Number:
AT32UC3A0256-ALUT
Manufacturer:
Atmel
Quantity:
10 000
36.9.4
32058J–AVR32–04/11
MEMORY_SIZED_ACCESS
For any operation, the full 7 bits of the address must be provided. For write operations, 32 data
bits must be provided, or the result will be undefined. For read operations, shifting may be termi-
nated once the required number of bits have been acquired.
Table 36-6.
This instruction allows access to the entire Service Access Bus data area. Data are accessed
through a 36-bit byte index, a 2-bit size, a direction bit, and 8, 16, or 32 bits of data. Not all units
mapped on the SAB bus may support all sizes of accesses, e.g. some may only support word
accesses.
The data register is alternately interpreted by the SAB as an address register and a data regis-
ter. The SAB starts in address mode after the MEMORY_SIZED_ACCESS instruction is
selected, and toggles between address and data mode each time a data scan completes with
the busy bit cleared.
The size field is encoded as i
Table 36-7.
Instructions
IR input value
IR output value
DR Size
DR input value (Address phase)
DR input value (Data read phase)
DR input value (Data write phase)
DR output value (Address phase)
DR output value (Data read phase)
DR output value (Data write phase)
Size field value
00
MEMORY_SERVICE details
Size Field Semantics
Access size
Byte (8 bits)
Table
36-7.
Details
10100 (0x14)
peb01
34 bits
aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx
dddddddd dddddddd dddddddd dddddddd xx
xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
eb dddddddd dddddddd dddddddd dddddddd
xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
Data alignment
Address modulo 4 : data alignment
0: dddddddd xxxxxxxx xxxxxxxx xxxxxxxx
1: xxxxxxxx dddddddd xxxxxxxx xxxxxxxx
2: xxxxxxxx xxxxxxxx dddddddd xxxxxxxx
3: xxxxxxxx xxxxxxxx xxxxxxxx dddddddd
AT32UC3A
753

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