ATMEGA128L-8AU Atmel, ATMEGA128L-8AU Datasheet

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... ATmega103 Compatibility Mode Selected by a Fuse – Global Pull-up Disable • I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V ATmega128L – 4.5 - 5.5V ATmega128 • Speed Grades – 8MHz ATmega128L – 16MHz ATmega128 ® ® ...

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... PB3 (OC0) PB4 (OC1A) PB5 (OC1B) PB6 Note: Overview The Atmel enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega128 achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ATmega128 2 ...

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Block Diagram Figure 2. Block Diagram PF0 - PF7 VCC GND PORTF DRIVERS DATA REGISTER PORTF REG. PORTF AVCC ADC AGND AREF PROGRAM JTAG TAP COUNTER PROGRAM ON-CHIP DEBUG FLASH BOUNDARY- INSTRUCTION SCAN REGISTER PROGRAMMING PEN INSTRUCTION LOGIC DECODER CONTROL ...

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... Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega128 is a powerful microcontroller that provides a highly flexible and cost effec- tive solution to many embedded control applications. The ATmega128 device is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits ...

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... ATmega103 By programming the M103C fuse, the Atmel Compatibility Mode ATmega103 regards to RAM, I/O pins and interrupt vectors as described above. However, some new features in ATmega128 are not available in this compatibility mode, these features are listed below: • One USART instead of two, Asynchronous mode only. Only the eight least significant bits of the Baud Rate Register is available. • ...

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... The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the Atmel page 76. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri- stated when a reset condition becomes active ...

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RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in 50. Shorter pulses are not guaranteed ...

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... Resources A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C ...

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Register Summary Address Name Bit 7 ($FF) Reserved – .. Reserved – ($9E) Reserved – ($9D) UCSR1C – ($9C) UDR1 ($9B) UCSR1A RXC1 ($9A) UCSR1B RXCIE1 ($99) UBRR1L ($98) UBRR1H – ($97) Reserved – ($96) Reserved – ($95) UCSR0C – ...

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Register Summary (Continued) Address Name Bit 7 ($61) DDRF DDF7 ($60) Reserved – $3F ($5F) SREG I $3E ($5E) SPH SP15 $3D ($5D) SPL SP7 $3C ($5C) XDIV XDIVEN $3B ($5B) RAMPZ – $3A ($5A) EICRB ISC71 $39 ($59) EIMSK ...

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Register Summary (Continued) Address Name Bit 7 $01 ($21) PINE PINE7 $00 ($20) PINF PINF7 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. ...

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Instruction Set Summary Mnemonics Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...

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Instruction Set Summary (Continued) Mnemonics Operands Description BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate LD ...

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Instruction Set Summary (Continued) Mnemonics Operands Description SEV Set Twos Complement Overflow. CLV Clear Twos Complement Overflow SET Set T in SREG CLT Clear T in SREG SEH Set Half Carry Flag in SREG Clear Half Carry Flag in SREG ...

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... Tape and Reel 64A 64-lead 1.0mm, Thin Profile Plastic Quad Flat Package (TQFP) 64M1 64-pad 1.0mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 2467VS–AVR–02/11 (1) Ordering Code Package ATmega128L-8AU 64A ATmega128L-8MU 64M1 ATmega128-16AU 64A ATmega128-16MU 64M1 ATmega128L–8AN 64A (3) ATmega128L– ...

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Packaging Information 64A PIN 0°~7° Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are ...

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Marked Pin TOP VIEW BOTTOM VIEW Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. 2325 Orchard Parkway San Jose, CA 95131 R 2467VS–AVR–02/11 ...

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Errata The revision letter in this section refers to the revision of the ATmega128 device. ATmega128 Rev • First Analog Comparator conversion may be delayed • Interrupts may be lost when writing the timer registers in the ...

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SEI 4. Stabilizing time needed when changing OSCCAL Register After increasing the source clock frequency more than 2% with settings in the OSCCAL reg- ister, the device may execute some of the subsequent instructions incorrectly. Problem Fix / Workaround The ...

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... History Rev. 2467V-02/11 1. Updated the literature number (2467) that accidently changed in rev U. 2. Editing update according to the Atmel new style guide. No more space betweeen the numbers and their units. 3. Reorganized the swapped chapters in rev U: 8-bit Timer/Counter 0, 16-bit TC1 and TC3, and 8-bit TC2 with PWM. ...

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... ATmega128L removed from 6. Added 7. Updated Pb-Plated packages are no longer offered, and the ordering information for these packages are removed. There will no longer exist separate ordering codes for commercial operation range, only industrial operation range. 8. Updated Merged errata description for rev.F to rev.M in Rev ...

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Updated 8. Updated Features in 9. Added note in 10. Updated Rev. 2467M-11/04 1. Removed “analog ground”, replaced by “ground”. 2. Updated Table 132 on page 3. Added note to 4. Updated Rev. 2467L-05/04 1. Removed “Preliminary” and “TBD” ...

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Updated R 8. Added a proposal for solving problems regarding the JTAG instruction IDCODE in “Errata” on page Rev. 2467H-02/03 1. Corrected the names of the two Prescaler bits in the SFIOR Register. 2. Added Chip Erase as a ...

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Correct PWM Mode” on page 100 “Fast PWM Mode” on page 151 “Phase Correct PWM Mode” on page 152 8. Corrected 9. Corrected 10. Updated Vil parameter in Rev. 2467E-04/02 1. Updated the Characterization Data in Section 2. Updated ...

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Added Calibrated RC Oscillator characterization curves in section teristics” on page 13. Updated More details regarding use of the TWI Power-down operation and using the TWI as master with low TWBRR values are added into the data sheet. Added ...

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