P89LPC932A1FDH,512 NXP Semiconductors, P89LPC932A1FDH,512 Datasheet - Page 27

• Manufacturer Part Number: P89LPC932A1FDH,512
• Description: IC 80C51 MCU FLASH 8K 28-TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC932A1FDH,512

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 28-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 26
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC9x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Cpu Family: 89LP
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 18MHz
• Total Internal Ram Size: 768Byte
• # I/os (max): 26
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.4V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM6292 - DEMO BOARD PCA2125 RTCDB-TSSOP-LPC932 - BOARD FOR LPC932 TSSOP622-1014 - BOARD FOR LPC9XX TSSOP622-1008 - BOARD FOR LPC9103 10-HVSON622-1006 - SOCKET ADAPTER BOARDMCB900K - BOARD PROTOTYPE NXP 89LPC9EPM900K - EMULATOR/PROGRAMMER NXP P89LPC9568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART622-1003 - KIT FOR LCD DEMO622-1002 - USB IN-CIRCUIT PROG LPC9XX568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4515-5; 935276132512; P89LPC932A1FDH; P89LPC932A1FDH

NXP Semiconductors
P89LPC932A1_3
Product data sheet
7.19.1 CCU clock
7.19.2 CCUCLK prescaling
7.19.3 Basic timer operation
7.19.4 Output compare
7.19.5 Input capture
7.19 CCU
This unit features:
The CCU runs on the CCU Clock (CCUCLK), which is either PCLK in basic timer mode, or
the output of a Phase-Locked Loop (PLL). The PLL is designed to use a clock source
between 0.5 MHz to 1 MHz that is multiplied by 32 to produce a CCUCLK between
16 MHz and 32 MHz in PWM mode (asymmetrical or symmetrical). The PLL contains a
4-bit divider to help divide PCLK into a frequency between 0.5 MHz and 1 MHz.
This CCUCLK can further be divided down by a prescaler. The prescaler is implemented
as a 10-bit free-running counter with programmable reload at overflow.
The Timer is a free-running up/down counter with a direction control bit. If the timer
counting direction is changed while the counter is running, the count sequence will be
reversed. The timer can be written or read at any time.
When a reload occurs, the CCU Timer Overflow Interrupt Flag will be set, and an interrupt
generated if enabled. The 16-bit CCU Timer may also be used as an 8-bit up/down timer.
There are four output compare channels A, B, C and D. Each output compare channel
needs to be enabled in order to operate and the user will have to set the associated I/O
pin to the desired output mode to connect the pin. When the contents of the timer matches
that of a capture compare control register, the Timer Output Compare Interrupt Flag
(TOCFx) becomes set. An interrupt will occur if enabled.
Input capture is always enabled. Each time a capture event occurs on one of the two input
capture pins, the contents of the timer is transferred to the corresponding 16-bit input
capture register. The capture event can be programmed to be either rising or falling edge
triggered. A simple noise filter can be enabled on the input capture by enabling the Input
Capture Noise Filter bit. If set, the capture logic needs to see four consecutive samples of
the same value in order to recognize an edge as a capture event. An event counter can be
set to delay a capture by a number of capture events.
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A 16-bit timer with 16-bit reload on overflow.
Selectable clock, with prescaler to divide clock source by any integral number
between 1 and 1024.
Four Compare/PWM outputs with selectable polarity
Symmetrical/Asymmetrical PWM selection
Two Capture inputs with event counter and digital noise rejection filter
Seven interrupts with common interrupt vector (one Overflow, two Capture,
four Compare)
Safe 16-bit read/write via shadow registers.
Rev. 03 — 12 March 2007
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC932A1
© NXP B.V. 2007. All rights reserved.
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