IC ARM CORTEX MCU 128K 80-LQFP

LPC1754FBD80,551

Manufacturer Part NumberLPC1754FBD80,551
DescriptionIC ARM CORTEX MCU 128K 80-LQFP
ManufacturerNXP Semiconductors
SeriesLPC17xx
LPC1754FBD80,551 datasheets
 


Specifications of LPC1754FBD80,551

Program Memory TypeFLASHProgram Memory Size128KB (128K x 8)
Package / Case80-LQFPCore ProcessorARM® Cortex-M3™
Core Size32-BitSpeed100MHz
ConnectivityCAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTGPeripheralsBrown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o52Ram Size32K x 8
Voltage - Supply (vcc/vdd)2.4 V ~ 3.6 VData ConvertersA/D 6x12b, D/A 1x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesLPC17CoreARM Cortex M3
Data Bus Width32 bitData Ram Size32 KB
Interface TypeCAN, I2C, SPI, UARTMaximum Clock Frequency100 MHz
Number Of Programmable I/os52Number Of Timers3
Operating Supply Voltage3.3 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsMDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature- 40 COn-chip Adc12 bit, 6 Channel
On-chip Dac10 bitCpu FamilyLPC17xx
Device CoreARM Cortex-M3Device Core Size32b
Frequency (max)100MHzTotal Internal Ram Size32KB
# I/os (max)52Number Of Timers - General Purpose4
Operating Supply Voltage (typ)3.3VOperating Supply Voltage (max)3.6V
Operating Supply Voltage (min)2.4/2.7VInstruction Set ArchitectureRISC
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count80
Package TypeLQFPLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use With622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2KEeprom Size-
Other names568-4790
935287913551
  
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LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB
SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN
Rev. 6.01 — 11 March 2011
1. General description
The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded
applications featuring a high level of integration and low power consumption. The ARM
Cortex-M3 is a next generation core that offers system enhancements such as enhanced
debug features and a higher level of support block integration.
The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100 MHz. The
LPC1759 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU
incorporates a 3-stage pipeline and uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3
CPU also includes an internal prefetch unit that supports speculative branching.
The peripheral complement of the LPC1759/58/56/54/52/51 includes up to 512 kB of flash
memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface,
8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers,
SPI interface, 2 I
12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general
purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC)
with separate battery supply, and up to 52 general purpose I/O pins.
2. Features and benefits
ARM Cortex-M3 processor, running at frequencies of up to 100 MHz
(LPC1758/56/57/54/52/51) or of up to 120 MHz (LPC1759). A Memory Protection Unit
(MPU) supporting eight regions is included.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator
enables high-speed 120 MHz operation with zero wait states.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
On-chip SRAM includes:
Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance
CPU access.
Two/one 16 kB SRAM blocks with separate access paths for higher throughput.
These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA
memory, as well as for general purpose CPU instruction and data storage.
Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I
Digital-to-Analog converter peripherals, timer match signals, and for
memory-to-memory transfers.
2
C-bus interfaces, 2-input plus 2-output I
2
S-bus, UART, the Analog-to-Digital and
Product data sheet
2
S-bus interface, 6 channel

LPC1754FBD80,551 Summary of contents

  • Page 1

    LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 MCU 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN Rev. 6.01 — 11 March 2011 1. General description The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded applications featuring ...

  • Page 2

    ... NXP Semiconductors Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC (LPC1758 only), and the USB interface. This interconnect provides communication with no arbitration delays. Split APB bus allows high throughput with few stalls between the CPU and DMA. ...

  • Page 3

    ... NXP Semiconductors Repetitive Interrupt Timer (RIT) provides programmable and repeating timed interrupts. Each peripheral has its own clock divider for further power savings. Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options. ...

  • Page 4

    ... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name Description plastic low-profile quad package; 80 leads; body 12 × 12 × 1.4 mm LPC1759FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12 × 12 × 1.4 mm LPC1758FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12 × 12 × 1.4 mm ...

  • Page 5

    ... NXP Semiconductors 5. Block diagram debug JTAG port interface TEST/DEBUG INTERFACE ARM CORTEX-M3 I-code D-code bus bus slave P0, P1, HIGH-SPEED P2, P4 GPIO APB slave group 0 SCK1 SSEL1 SSP1 MISO1 MOSI1 RXD0/TXD0 UART0/1 8 × UART1 RD1/2 (1) CAN1/CAN2 TD1/2 SCL1 I2C1 SDA1 SCK/SSEL SPI0 MOSI/MISO 2 × ...

  • Page 6

    ... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin configuration LQFP80 package 6.2 Pin description Table 3. Pin description Symbol Pin Type P0[0] to P0[31] I/O [1] P0[0]/RD1/TXD3/ 37 I/O SDA1 I O I/O [1] P0[1]/TD1/RXD3/ 38 I/O SCL1 O I I/O [2] P0[2]/TXD0/AD0[ [2] P0[3]/RXD0/AD0[6] 80 I/O ...

  • Page 7

    ... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P0[7]/I2STX_CLK/ 63 I/O SCK1/MAT2[1] I/O I/O O [1] P0[8]/I2STX_WS/ 62 I/O MISO1/MAT2[2] I/O I/O O [1] P0[9]/I2STX_SDA/ 61 I/O MOSI1/MAT2[3] I/O I/O O [1] P0[10]/TXD2/ 39 I/O SDA2/MAT3[0] O I/O O [1] P0[11]/RXD2/ 40 I/O SCL2/MAT3[1] I I/O ...

  • Page 8

    ... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P0[22]/RTS1/TD1 44 I [2] P0[25]/AD0[2]/ 7 I/O I2SRX _SDA/ I TXD3 I/O O [3] P0[26]/AD0[3]/ 6 I/O AOUT/RXD3 [4] P0[29]/USB_D+ 22 I/O I/O [4] P0[30]/USB_D− 23 I/O I/O P1[0] to P1[31] I/O [1] P1[0]/ 76 I/O ENET_TXD0 O [1] P1[1]/ ...

  • Page 9

    ... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P1[19]/MCOA0/ 26 I/O USB_PPWR O CAP1[ [1] P1[20]/MCI0/ 27 I/O PWM1[2]/SCK0 I O I/O [1] P1[22]/MCOB0/ 28 I/O USB_PWRD/ O MAT1[ [1] P1[23]/MCI1/ 29 I/O PWM1[4]/MISO0 I O I/O [1] P1[24]/MCI2/ 30 I/O PWM1[5]/MOSI0 I O I/O [1] P1[25]/MCOA1/ ...

  • Page 10

    ... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [2] P1[30]/ I/O BUS AD0[ [2] P1[31]/SCK1/ 17 I/O AD0[5] I/O I P2[0] to P2[31] I/O [1] P2[0]/PWM1[1]/ 60 I/O TXD1 O O [1] P2[1]/PWM1[2]/ 59 I/O RXD1 O I [1] P2[2]/PWM1[3]/ 58 I/O CTS1/ O TRACEDATA[ [1] P2[3]/PWM1[4]/ 55 I/O DCD1/ O TRACEDATA[2] ...

  • Page 11

    ... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P2[8]/TD2/ 50 I/O TXD2 O O [1] P2[9]/ 49 I/O USB_CONNECT/ O RXD2 I [5] 41 I/O P2[10]/EINT0/NMI I I P4[0] to P4[31] I/O [1] P4[28]/RX_MCLK/ 65 I/O MAT2[0]/TXD3 [1] P4[29]/TX_MCLK/ 68 I/O MAT2[1]/RXD3 [6] TDO/SWO [7] TDI 2 I [7] TMS/SWDIO 3 I I/O ...

  • Page 12

    ... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type SSA V 21, 42, I DD(3V3 DD(REG)(3V3 DDA VREFP 10 I VREFN 12 I [11] VBAT tolerant pad providing digital I/O functions with TTL levels and hysteresis. [ tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant ...

  • Page 13

    ... NXP Semiconductors 7. Functional description 7.1 Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus (see system bus and are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices ...

  • Page 14

    ... NXP Semiconductors The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system. The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses ...

  • Page 15

    APB1 peripherals 0x4010 0000 31 system control 0x400F C000 reserved 0x400C 0000 15 QEI 0x400B C000 14 motor control PWM 0x400B 8000 ...

  • Page 16

    ... NXP Semiconductors 7.7 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.7.1 Features • Controls system exceptions and peripheral interrupts • ...

  • Page 17

    ... NXP Semiconductors 7.9.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. • ...

  • Page 18

    ... NXP Semiconductors Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode ...

  • Page 19

    ... NXP Semiconductors – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Cyclic Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. ...

  • Page 20

    ... NXP Semiconductors • While USB is in the Suspend mode, the LPC1759/58/56/54/52/51 can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints. • Allows dynamic switching between CPU-controlled slave and DMA modes. ...

  • Page 21

    ... NXP Semiconductors 7.13.1 Features • One or two CAN controllers and buses. • Data rates to 1 Mbit/s on each bus. • 32-bit register and RAM access. • Compatible with CAN specification 2.0B, ISO 11898-1. • Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit) receive identifiers for all CAN buses. • ...

  • Page 22

    ... NXP Semiconductors 7.16 UARTs The LPC1759/58/56/54/52/51 each contain four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. ...

  • Page 23

    ... NXP Semiconductors bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. ...

  • Page 24

    ... NXP Semiconductors 2 The I S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I master, and one slave. The I channel, each of which can operate as either a master or a slave. 7.20.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • ...

  • Page 25

    ... NXP Semiconductors • two match registers can be used to generate timed DMA requests. 7.22 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC1759/58/56/54/52/51. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers ...

  • Page 26

    ... NXP Semiconductors • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • ...

  • Page 27

    ... NXP Semiconductors 7.25 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals ...

  • Page 28

    ... NXP Semiconductors 7.28 RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC1759/58/56/54/52/51 is designed to have extremely low power consumption, i.e. less than 1 μA. The RTC will typically run from the main chip power supply, conserving battery power while the rest of the device is powered up ...

  • Page 29

    ... NXP Semiconductors LPC17xx MAIN OSCILLATOR system clock select (CLKSRCSEL) INTERNAL RC OSCILLATOR 32 kHz RTC rtclk = 1Hz OSCILLATOR Fig 4. LPC1759/58/56/54/52/51 clocking generation block diagram 7.29.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU ...

  • Page 30

    ... NXP Semiconductors 7.29.2 Main PLL (PLL0) The PLL0 accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input frequency is multiplied high frequency, then divided down to provide the actual clock used by the CPU and/or the USB block. The PLL0 input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value ‘ ...

  • Page 31

    ... NXP Semiconductors electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 7.29.5 Power control The LPC1759/58/56/54/52/51 support a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode ...

  • Page 32

    ... NXP Semiconductors On wake-up from Deep-sleep mode, the code execution and peripherals activities will resume after 4 cycles expire if the IRC was used before entering Deep-sleep mode. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. PLL and clock dividers need to be reconfigured accordingly. ...

  • Page 33

    ... NXP Semiconductors On the LPC1759/58/56/54/52/51, I/O pads are powered by the 3 the V DD(REG)(3V3) the CPU and most of the peripherals. Depending on the LPC1759/58/56/54/52/51 application, a design can use two power options to manage power consumption. The first option assumes that power consumption is not a concern and the design ties the ...

  • Page 34

    ... NXP Semiconductors V Fig 5. Power distribution 7.30 System control 7.30.1 Reset Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains ...

  • Page 35

    ... NXP Semiconductors 7.30.2 Brownout detection The LPC1759/58/56/54/52/51 include 2-stage monitoring of the voltage on the V DD(REG)(3V3) the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. ...

  • Page 36

    ... NXP Semiconductors 7.30.5 AHB multilayer matrix The LPC1759/58/56/54/52/51 use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these memories ...

  • Page 37

    ... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V regulator supply voltage (3.3 V) DD(REG)(3V3) V analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V input voltage on pin VREFP ...

  • Page 38

    ... NXP Semiconductors 9. Thermal characteristics 9.1 Thermal characteristics The average chip junction temperature, T equation amb • ambient temperature (°C), amb • the package junction-to-ambient thermal resistance (°C/W) th(j-a) • sum of internal and I/O power dissipation D The internal power dissipation is the product of I the I/O pins is often small and many times can be negligible. However it can be significant in some applications ...

  • Page 39

    ... NXP Semiconductors 10. Static characteristics Table 6. Static characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Supply pins V supply voltage (3.3 V) DD(3V3) V regulator supply voltage DD(REG)(3V3) (3 analog 3.3 V pad supply DDA voltage V input voltage on pin i(VBAT) VBAT V input voltage on pin ...

  • Page 40

    ... NXP Semiconductors Table 6. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter I ADC supply current DD(ADC) I ADC input current I(ADC) Standard port pins, RESET I LOW-level input current HIGH-level input IH current I OFF-state output OZ current V input voltage I V output voltage ...

  • Page 41

    ... NXP Semiconductors Table 6. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Oscillator pins V input voltage on pin i(XTAL1) XTAL1 V output voltage on pin o(XTAL2) XTAL2 V input voltage on pin i(RTCX1) RTCX1 V output voltage on pin o(RTCX2) RTCX2 USB pins I OFF-state output ...

  • Page 42

    ... NXP Semiconductors [15] The ADC is in Power-down mode if the PDN bit in the AD0CR register is set to 0. See LPC17xx user manual UM10360 °C. [16 3 i(VREFP) amb [17] Including voltage on outputs in 3-state mode. [18] V supply voltages must be present. DD(3V3) [19] 3-state outputs go into 3-state mode in Deep power-down mode. ...

  • Page 43

    ... NXP Semiconductors 120 I DD(Reg)(3V3) (μ −40 Conditions: V Fig 7. Power-down mode: Typical regulator supply current I temperature 1.8 I BAT) (μA) 1.4 1.0 0.6 -40 Conditions: V Fig 8. Deep power-down mode: Typical battery supply current I LPC1759_58_56_54_52_51 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller − 3.3 V ...

  • Page 44

    ... NXP Semiconductors 2.0 I DD(REG)(3V3) (µA) 1.6 1.2 0.8 0.4 0 Conditions: V Fig 9. Deep power-down mode: Typical regulator supply current I supply current I LPC1759_58_56_54_52_51 Product data sheet LPC1759/58/56/54/52/51 /I BAT - 3.0 V; RTC running. BAT DD(REG)(3V3) versus temperature BAT All information provided in this document is subject to legal disclaimers. ...

  • Page 45

    ... NXP Semiconductors 10.2 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the PCONP register. All other blocks are disabled and no code is executed. Measured on a typical sample ° ...

  • Page 46

    ... NXP Semiconductors 10.3 Electrical pin characteristics 3 (V) 3.2 2.8 2.4 2.0 0 Conditions: V Fig 10. Typical HIGH-level output voltage (mA Conditions: V Fig 11. Typical LOW-level output current I LPC1759_58_56_54_52_51 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller °C 25 °C −40 ° 3.3 V; standard port pins. DD(REG)(3V3) ...

  • Page 47

    ... NXP Semiconductors (μA) −10 −30 −50 −70 0 Conditions: V Fig 12. Typical pull-up current (μ −10 0 Conditions: V Fig 13. Typical pull-down current I LPC1759_58_56_54_52_51 Product data sheet LPC1759/58/56/54/52/ °C 25 °C −40 ° 3.3 V; standard port pins. DD(REG)(3V3) DD(3V3) versus input voltage °C 25 °C −40 °C ...

  • Page 48

    ... NXP Semiconductors 11. Dynamic characteristics 11.1 Flash memory Table 8. Flash characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter N endurance endu t retention time ret t erase time er t programming time prog [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. ...

  • Page 49

    ... NXP Semiconductors 11.3 Internal oscillators Table 10. Dynamic characteristic: internal oscillators − ° ° ≤ + amb DD(3V3) Symbol Parameter f internal RC oscillator frequency osc(RC) f RTC input frequency i(RTC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. ...

  • Page 50

    ... NXP Semiconductors 2 11.5 I C-bus Table 12. Dynamic characteristic: I − ° +85 amb Symbol f SCL LOW t HIGH t HD;DAT t SU;DAT 2 [1] See the I C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. [ the data hold time that is measured from the falling edge of SCL; applies to data in transmission HD ...

  • Page 51

    ... NXP Semiconductors SDA HD;DAT SCL SCL 2 Fig 16. I C-bus pins clock timing LPC1759_58_56_54_52_51 Product data sheet LPC1759/58/56/54/52/51 t SU;DAT HIGH LOW All information provided in this document is subject to legal disclaimers. Rev. 6.01 — 11 March 2011 32-bit ARM Cortex-M3 microcontroller t VD;DAT 002aaf425 © NXP B.V. 2011. All rights reserved. ...

  • Page 52

    ... NXP Semiconductors 2 11.6 I S-bus interface (LPC1759/58/56 only) Table 13. Dynamic characteristics: I − ° ° +85 C. amb Symbol Parameter common to input and output t rise time r t fall time f t pulse width HIGH WH t pulse width LOW WL output t data output valid time v(Q) input ...

  • Page 53

    ... NXP Semiconductors I2SRX_CLK I2SRX_SDA I2SRX_WS 2 Fig 18. I S-bus timing (input) LPC1759_58_56_54_52_51 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller T cy(clk su(D) t su(D) All information provided in this document is subject to legal disclaimers. Rev. 6.01 — 11 March 2011 h(D) 002aae159 t su(D) © NXP B.V. 2011. All rights reserved. ...

  • Page 54

    ... NXP Semiconductors 11.7 SSP interface Table 14. Dynamic characteristic: SSP interface ° over specified ranges. amb DD(3V3) Symbol Parameter t SPI_MISO set-up time su(SPI_MISO) [1] The peripheral clock for SSP is PCLK = CCLK = 20 MHz. shifting edges SCK MOSI MISO Fig 19. SSP MISO line set-up time in SPI Master mode ...

  • Page 55

    ... NXP Semiconductors 11.8 USB interface Table 15. Dynamic characteristics: USB pins (full-speed) Ω pF 1 DD(3V3) Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT t source jitter for differential transition ...

  • Page 56

    ... NXP Semiconductors 11.9 SPI Table 16. Dynamic characteristics of SPI pins − ° +85 amb Symbol Parameter T PCLK cycle time cy(PCLK) T SPI cycle time SPICYC t SPICLK HIGH time SPICLKH t SPICLK LOW time SPICLKL SPI master t SPI data set-up time SPIDSU t SPI data hold time ...

  • Page 57

    ... NXP Semiconductors Fig 22. SPI master timing (CPHA = 0) SCK (CPOL = 0) SCK (CPOL = 1) Fig 23. SPI slave timing (CPHA = 1) LPC1759_58_56_54_52_51 Product data sheet LPC1759/58/56/54/52/51 T SPICYC SCK (CPOL = 0) SCK (CPOL = 1) t SPIQV DATA VALID MOSI t DATA VALID MISO T SPICYC MOSI DATA VALID t SPIQV MISO DATA VALID All information provided in this document is subject to legal disclaimers. Rev. 6.01 — ...

  • Page 58

    ... NXP Semiconductors Fig 24. SPI slave timing (CPHA = 0) 12. ADC electrical characteristics Table 17. ADC characteristics (full resolution) − ° 2 3 +85 DDA amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error ...

  • Page 59

    ... NXP Semiconductors Table 18. ADC characteristics (lower resolution) − ° ° +85 C unless otherwise specified; 12-bit ADC used as 10-bit resolution ADC. amb Symbol Parameter E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G f ADC clock frequency clk(ADC) ADC conversion frequency 3 V ≤ V ...

  • Page 60

    ... NXP Semiconductors 4095 4094 4093 4092 4091 4090 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 25. 12-bit ADC characteristics LPC1759_58_56_54_52_51 Product data sheet ...

  • Page 61

    ... NXP Semiconductors COMPARATOR The values of resistor components R process-dependent (see Parasitic resistance and capacitance from the pad are not included in this figure. Fig 26. ADC interface to pins AD0[n] Table 19. ADC interface components Component 13. DAC electrical characteristics (LPC1759/58/56/54 only) Table 20. DAC electrical characteristics − ...

  • Page 62

    ... NXP Semiconductors 14. Application information 14.1 Suggested USB interface solutions LPC17xx Fig 27. LPC1759/58/56/54/52/51 USB interface on a self-powered device LPC17xx Fig 28. LPC1759/58/56/54/52/51 USB interface on a bus-powered device LPC1759_58_56_54_52_51 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller V DD(3V3) USB_UP_LED USB_CONNECT SoftConnect switch R1 1.5 kΩ ...

  • Page 63

    ... NXP Semiconductors RSTOUT LPC1759/58/ SCL1/2 56/54 SDA1/2 EINT0 USB_D+ USB_D− USB_UP_LED Fig 29. LPC1759/58/56/54 USB OTG port configuration USB_UP_LED USB_D+ USB_D− LPC1759/58/ 56/54 USB_PWRD USB_PPWR Fig 30. LPC1759/58/56/54 USB host port configuration LPC1759_58_56_54_52_51 Product data sheet LPC1759/58/56/54/52/ RESET_N ADR/PSW OE_N/INT_N V DD ...

  • Page 64

    ... NXP Semiconductors USB_UP_LED USB_CONNECT LPC17xx USB_D+ USB_D− V BUS Fig 31. LPC1759/58/56/54/52/51 USB device port configuration 14.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF ...

  • Page 65

    ... NXP Semiconductors Fig 33. Oscillator modes and models: oscillation mode of operation and external crystal model used for C Table 21. Recommended values for C components parameters): low frequency mode Fundamental oscillation frequency F OSC 1 MHz - 5 MHz 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 22. Recommended values for C ...

  • Page 66

    ... NXP Semiconductors order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C accordingly to the increase in parasitics of the PCB layout. 14.4 Standard I/O pin configuration Figure 34 shows the possible pin modes for standard I/O pins with analog input function: • ...

  • Page 67

    ... NXP Semiconductors 14.5 Reset pin configuration reset Fig 35. Reset pin configuration LPC1759_58_56_54_52_51 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 6.01 — 11 March 2011 ESD PIN ESD V SS 002aaf274 © NXP B.V. 2011. All rights reserved. ...

  • Page 68

    ... NXP Semiconductors 15. Package outline LQFP80: plastic low profile quad flat package; 80 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.16 1.5 0.27 mm 1.6 0.25 0.04 1.3 0.13 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

  • Page 69

    ... NXP Semiconductors 16. Abbreviations Table 23. Abbreviations Acronym ADC AHB AMBA APB BOD CAN DAC DMA EOP GPIO IRC IrDA JTAG MAC MIIM OTG PHY PLL PWM RMII SE0 SPI SSI SSP TTL UART USB LPC1759_58_56_54_52_51 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller ...

  • Page 70

    ... NXP Semiconductors 17. Revision history Table 24. Revision history Document ID Release date LPC1759_58_56_54_52_51 <tbd> v.6.01 • Modifications: • • • • LPC1759_58_56_54_52_51 v.6 <tbd> • Modifications: • LPC1759_58_56_54_52_51 v.5 20100716 LPC1759_58_56_54_52_51 v.4 20100126 LPC1758_56_54_52_51 v.3 20091119 LPC1758_56_54_52_51 v.2 20090211 LPC1758_56_54_52_51 v.1 20090115 LPC1759_58_56_54_52_51 ...

  • Page 71

    ... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

  • Page 72

    ... Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. ...

  • Page 73

    ... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . 13 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 13 7.2 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 13 7.3 On-chip flash program memory . . . . . . . . . . . 13 7 ...

  • Page 74

    ... NXP Semiconductors 13 DAC electrical characteristics (LPC1759/58/56/54 only Application information 14.1 Suggested USB interface solutions . . . . . . . . 61 14.2 Crystal oscillator XTAL input and component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 14.3 XTAL Printed-Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 14.4 Standard I/O pin configuration . . . . . . . . . . . . 65 14.5 Reset pin configuration . . . . . . . . . . . . . . . . . . 66 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 67 16 Abbreviations ...