LPC1754FBD80,551 NXP Semiconductors, LPC1754FBD80,551 Datasheet - Page 33

IC ARM CORTEX MCU 128K 80-LQFP

LPC1754FBD80,551

Manufacturer Part Number
LPC1754FBD80,551
Description
IC ARM CORTEX MCU 128K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets

Specifications of LPC1754FBD80,551

Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
52
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Cpu Family
LPC17xx
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
100MHz
Total Internal Ram Size
32KB
# I/os (max)
52
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2.4/2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4790
935287913551

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NXP Semiconductors
LPC1759_58_56_54_52_51
Product data sheet
On the LPC1759/58/56/54/52/51, I/O pads are powered by the 3.3 V (V
the V
the CPU and most of the peripherals.
Depending on the LPC1759/58/56/54/52/51 application, a design can use two power
options to manage power consumption.
The first option assumes that power consumption is not a concern and the design ties the
V
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (V
a dedicated 3.3 V supply for the CPU (V
powered independently from the I/O pad ring enables shutting down of the I/O pad power
supply “on the fly”, while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of
power to operate, which can be supplied by an external battery. The device core power
(V
there is no power drain from the RTC battery when V
DD(3V3)
DD(REG)(3V3)
DD(REG)(3V3)
and V
) is used to operate the RTC whenever V
DD(REG)(3V3)
All information provided in this document is subject to legal disclaimers.
pin powers the on-chip voltage regulator which in turn provides power to
Rev. 6.01 — 11 March 2011
pins together. This approach requires only one 3.3 V power
LPC1759/58/56/54/52/51
DD(REG)(3V3)
32-bit ARM Cortex-M3 microcontroller
). Having the on-chip voltage regulator
DD(REG)(3V3)
DD(REG)(3V3)
is available.
is present. Therefore,
DD(3V3)
© NXP B.V. 2011. All rights reserved.
) pins, while
DD(3V3)
33 of 74
) and

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