LPC3250FET296/01,5 NXP Semiconductors, LPC3250FET296/01,5 Datasheet
LPC3250FET296/01,5
Specifications of LPC3250FET296/01,5
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LPC3250FET296/01,5 Summary of contents
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LPC3220/30/40/50 16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface Rev. 01 — 6 February 2009 1. General description The LPC3220/30/40/50 embedded microcontrollers were designed for low power, high performance applications. NXP achieved their performance goals using ...
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... NXP Semiconductors I External memory controller for DDR and SDR SDRAM as well as for static devices. I Two NAND flash controllers: One for single-level NAND flash devices and the other for multi-level NAND flash devices. I Master Interrupt Controller (MIC) and two Slave Interrupt Controllers (SIC), supporting 74 interrupt sources ...
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... NXP Semiconductors N WatchDog timer clocked by the peripheral clock. N Two single-output PWM blocks. N Motor control PWM N Keyboard scanner function allows automatic scanning external interrupts. I Standard ARM test/debug interface for compatibility with existing tools. I Emulation Trace Buffer (ETB) with 2048 I Stop mode saves power while allowing many peripheral functions to restart CPU activity ...
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... NXP Semiconductors 5. Block diagram ETB ETM 9 VFP9 D-CACHE ARM I-CACHE 32 kB 9EJS 32 kB D-SIDE I-SIDE MMU CONTROLLER CONTROLLER DATA INSTRUCTION master layer slave port bit, AHB matrix = Master/Slave connection supported by the multilayer AHB matrix Fig 1. Block diagram of LPC3220/30/40/50 LPC3220_30_40_50_1 Preliminary data sheet ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Table 3. Pin allocation table (TFBGA296) Pin Symbol Row A A4 I2S1TX_CLK/MAT3[0] A7 MS_DIO1/MAT0[1] A10 SPI2_DATIN/MISO1/LCDVD[21]/ GPI_27 A13 GPO_21/U4_TX/LCDVD[3] A16 GPO_6/LCDVD[18] Row B B4 I2S1TX_WS/CAP3[0] B7 MS_SCLK/MAT2[0] B10 SPI2_CLK/SCK1/LCDVD[23] B13 GPO_13/MCOB1/LCDDCLK B16 GPI_8/KEY_COL6/ SPI2_BUSY/ENET_RX_DV Row C C1 FLASH_RD C4 USB_ATX_INT C7 GPI_6/HSTIM_CAP/ ...
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... NXP Semiconductors Table 3. Pin allocation table (TFBGA296) Pin Symbol C10 SPI1_DATIN/MISO0/GPI_25/ MCI1 C13 GPO_8/LCDVD[8] C16 GPI_0/I2S1RX_SDA Row D D1 FLASH_RDY D4 GPO_1 D7 P0[1]/I2S1RX_WS D10 GPO_16/MCOB0/LCDENAB/ LCDM D13 GPI_7/CAP4[0]/MCABORT D16 KEY_ROW3/ENET_TX_EN Row E E1 FLASH_IO[3] E4 I2C2_SDA E7 I2S1TX_SDA/MAT3[1] E10 GPO_22/U7_HRTS/LCDVD[14] E13 GPI_4/SPI1_BUSY E16 KEY_COL1/ENET_RX_CLK/ ...
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... NXP Semiconductors Table 3. Pin allocation table (TFBGA296) Pin Symbol H16 HIGHCORE/LCDVD[17] Row J J1 EMC_A[20]/P1[20] J4 EMC_A[23]/P1[23] J7 VDD_CORE J13 VDD_IOA J16 JTAG_TDI Row K K1 EMC_A[19]/P1[19] K4 EMC_A[17]/P1[17] K7 VDD_EMC K13 VSS_IOA K16 U1_TX Row L L1 EMC_A[15]/P1[15] L4 EMC_A[1]/P1[1] L7 VSS_CORE L13 VDD_RTCCORE ...
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... NXP Semiconductors Table 3. Pin allocation table (TFBGA296) Pin Symbol P7 VSS_EMC P10 VSS_EMC P13 VSS_AD P16 RTCX_IN Row R R1 EMC_A[13]/P1[13] R4 EMC_WR R7 EMC_D[1] R10 EMC_D[24]/P2[5] R13 TS_XP R16 VSS_PLLUSB Row T T1 EMC_DQM[2] T4 EMC_CLKIN T7 EMC_D[11] T10 EMC_D[23]/P2[4] T13 EMC_BLS[1] T16 VDD_PLL397 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin DBGEN G14 EMC_A[0]/P1[0] L3 EMC_A[1]/P1[1] L4 EMC_A[2]/P1[2] M1 EMC_A[3]/P1[3] M2 EMC_A[4]/P1[4] M3 EMC_A[5]/P1[5] N1 EMC_A[6]/P1[6] N2 EMC_A[7/P1[7] N3 EMC_A[8]/P1[8] M4 EMC_A[9]/P1[9] P1 EMC_A[10]/P1[10] P2 EMC_A[11]/P1[11] P3 EMC_A[12]/P1[12] N4 EMC_A[13]/P1[13] R1 EMC_A[14]/P1[14] R2 EMC_A[15]/P1[15] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin EMC_A[19]/P1[19] K1 EMC_A[20]/P1[20] J1 EMC_A[21]/P1[21] J2 EMC_A[22]/P1[22] J3 EMC_A[23]/P1[23] J4 EMC_BLS[0] U14 EMC_BLS[1] T13 EMC_BLS[2] R12 EMC_BLS[3] P12 EMC_CAS R5 EMC_CKE0 U3 EMC_CKE1 L2 EMC_CLK T3 EMC_CLKIN T4 EMC_CS0 U13 EMC_CS1 R11 EMC_CS2 T12 EMC_CS3 V15 EMC_D[0] U4 EMC_D[1] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin EMC_D[16]/ V8 EMC_DQS0 EMC_D[17]/ R9 EMC_DQS1 EMC_D[18]/ V9 EMC_CLK EMC_D[19]/P2[0] U9 EMC_D[20]/P2[1] T9 EMC_D[21]/P2[2] V10 EMC_D[22]/P2[3] U10 EMC_D[23]/P2[4] T10 EMC_D[24]/P2[5] R10 EMC_D[25]/P2[6] V11 EMC_D[26]/P2[7] U11 EMC_D[27]/P2[8] T11 EMC_D[28]/P2[9] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin EMC_WR R4 FLASH_ALE D2 FLASH_CE E3 FLASH_CLE F3 FLASH_IO[0] H2 FLASH_IO[1] H3 FLASH_IO[2] F1 FLASH_IO[3] E1 FLASH_IO[4] H4 FLASH_IO[5] G2 FLASH_IO[6] G3 FLASH_IO[7] E2 FLASH_RD C1 FLASH_RDY D1 FLASH_WR F2 GPI_0/I2S1RX_SDA C16 GPI_1/SERVICE C15 GPI_2/CAP2[0]/ C14 ENET_RXD3 GPI_3 F4 GPI_4/SPI1_BUSY E13 GPI_5/U3_DCD N16 GPI_6/ C7 HSTIM_CAP/ ENET_RXD2 GPI_7/CAP4[0]/ D13 MCABORT ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin GPI_19/U4_RX B15 GPI_28/U3_RI N17 GPIO_0 A12 GPIO_1 A11 GPIO_2/ D9 KEY_ROW6/ ENET_MDC GPIO_3/ C11 KEY_ROW7/ ENET_MDIO GPIO_4/ B11 SSEL1/ LCDVD[22] GPIO_5/ E9 SSEL0/ MCI0 GPO_0/ C3 TST_CLK1 GPO_1 D4 GPO_2/ B14 MAT1[0]/ LCDVD[0] GPO_3/ D12 LCDVD[1] GPO_4 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin GPO_12/ B12 MCOA2/ LCDLE GPO_13/ B13 MCOB1/ LCDDCLK GPO_14 D3 GPO_15/ A14 MCOA1/ LCDFP GPO_16/ D10 MCOB0/ LCDENAB/LCDM GPO_17 N18 GPO_18/ D11 MCOA0/ LCDLP GPO_19 C2 GPO_20 B2 GPO_21/ A13 U4_TX/ LCDVD[3] GPO_22/ E10 U7_HRTS/ LCDVD[14] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin JTAG_NTRST H17 JTAG_RTCK H18 JTAG_TCK H14 JTAG_TDI J16 JTAG_TDO J15 JTAG_TMS G18 KEY_COL0/ F15 ENET_TX_CLK KEY_COL1/ E16 ENET_RX_CLK/ ENET_REF_CLK KEY_COL2/ D17 ENET_RX_ER KEY_COL3/ D18 ENET_CRS KEY_COL4/ G15 ENET_RXD0 KEY_COL5/ F16 ENET_RXD1 KEY_ROW0/ E15 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin MS_DIO3/ C8 MAT0[3] MS_SCLK/ B7 MAT2[0] n.c. B17, U17, U2 ONSW M15 P0[0]/ B5 I2S1RX_CLK P0[1]/ D7 I2S1RX_WS P0[2]/ M17 I2S0RX_SDA/ LCDVD[4] P0[3]/ M18 I2S0RX_CLK/ LCDVD[5] P0[4]/ L15 I2S0RX_WS/ LCDVD[6] P0[5]/ L16 I2S0TX_SDA/ LCDVD[7] P0[6]/ L17 I2S0TX_CLK/ LCDVD[12] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin SPI1_CLK/ C9 SCK0 SPI1_DATIN/ C10 MISO0/ GPI_25/ MCI1 SPI1_DATIO/ B9 MOSI0/ MCI2 SPI2_CLK/ B10 SCK1/ LCDVD[23] SPI2_DATIO/ A9 MOSI1/ LCDVD[20] SPI2_DATIN/ A10 MISO1/ LCDVD[21]/ GPI_27 SYSCLKEN/ G17 LCDVD[15] SYSX_IN T17 SYSX_OUT R15 TS_XP R13 TS_YP U16 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin U3_TX J17 U5_RX/ F18 GPI_20 U5_TX H15 U6_IRRX/ F17 GPI_21 U6_IRTX G16 U7_HCTS/ G13 CAP0[1]/ LCDCLKIN/ GPI_22 U7_RX/ E17 CAP0[0]/ LCDVD[10]/ GPI_23 U7_TX/ E18 MAT1[1]/ LCDVD[11] USB_ATX_INT C4 USB_DAT_VP/ D5 U5_RX USB_I2C_SCL E5 USB_I2C_SDA E6 USB_OE_TP D6 USB_SE0_VM/ ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin VDD_EMC J6, K6, K7, L6, M6, M8, N7, N8, N9 N10, N11 VDD_IOA H13, J13 VDD_IOB F8 VDD_IOC F7, G6, H6, J5 VDD_IOD F13, F9 VDD_OSC T18 VDD_PLL397 T16 VDD_PLLHCLK R17 VDD_PLLUSB P15 VDD_FUSE N14 VDD_RTC K14 VDD_RTCCORE L13 VDD_RTCOSC N15 VSS_AD ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin VSS_IOB F6 VSS_IOC F5, G5, H5 VSS_IOD F10, F11, F12, H12 VSS_OSC P14 VSS_PLL397 T15 VSS_PLLHCLK R18 VSS_PLLUSB R16 VSS_RTCCORE L14 VSS_RTCOSC P18 [1] The PWM2_CTRL register controls this pin function (see LPC32x0 User manual ). Table 5. Parameter ...
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... NXP Semiconductors 7. Functional description 7.1 CPU and subsystems 7.1.1 CPU NXP created the LPC3220/30/40/50 using an ARM926EJ-S CPU core that includes a Harvard architecture and a 5-stage pipeline. To this ARM core, NXP implemented instruction cache data cache and a Vector Floating Point coprocessor. The ARM926EJ-S core also has an integral Memory Management Unit (MMU) to provide the virtual memory capabilities required to support the multi-programming demands of modern operating systems ...
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... NXP Semiconductors 7.1.3.2 Embedded trace buffer The Embedded Trace Module (ETM) is connected directly to the ARM core. It compresses the trace information and exports it through a narrow trace port. An internal Embedded Trace Buffer (ETB) of 2048 debugger control. Data from the ETB is recovered by the debug software through the JTAG port ...
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... NXP Semiconductors 7.2.1 APB Many peripheral functions are accessed by on-chip APBs that are attached to the higher speed AHB. The APB performs reads and writes to peripheral registers in three peripheral clocks. 7.2.2 FAB Some peripherals are placed on a special bus called FAB that allows faster CPU access to those peripheral functions ...
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... NXP Semiconductors off-chip memory peripherals on AHB matrix slave port 7 peripherals on AHB matrix slave port 6 peripherals on AHB matrix slave port 5 on-chip memory Fig 3. LPC3220_30_40_50_1 Preliminary data sheet 4.0 GB 2.0 GB APB peripherals FAB peripherals 1.0 GB AHB peripherals 768 MB AHB peripherals APB peripherals AHB peripherals ...
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... NXP Semiconductors 7.4 Internal memory 7.4.1 On-chip ROM The built- ROM contains a program which runs a boot procedure to load code from one of four external sources, UART5, SSP0 (SPI mode), EMC Static CS0 memory, or NAND FLASH. After reset, execution always begins from the internal ROM. The bootstrap software first reads the SERVICE input (GPI_1) ...
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... NXP Semiconductors 7.5.1.2 Single-Level Cell (SLC) NAND flash controller The SLC NAND flash controller interfaces to single-level NAND flash devices. DMA page transfers are supported, including a 20 byte DMA read and write FIFO. Hardware support for ECC (Error Checking and Correction) is included for the main data area. Software can correct a single bit error ...
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... NXP Semiconductors – extended wait • Power-saving modes dynamically control MPMCCKEOUT and MPMCCLKOUT. • Dynamic memory self-refresh mode supported by software. • Controller supports and 8 k row address synchronous memory parts. That is, typical 512 MB, 256 MB, 128 MB, and 16 MB parts, with 8, 16 data bits per device. • ...
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... NXP Semiconductors packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet DMA can access off-chip memory via the EMC, as well as the IRAM. The Ethernet block interfaces between an off-chip Ethernet PHY using the Media Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus ...
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... NXP Semiconductors condition is indicated via status registers. An interrupt is also generated if enabled. The DMA controller when enabled transfers data between the endpoint buffer and the USB RAM. Features • Fully compliant with USB 2.0 full-speed specification . • Supports 32 physical (16 logical) endpoints. ...
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... NXP Semiconductors • Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for dual-role devices under software control. HNP is partially implemented in hardware. • Provides programmable timers required for HNP and SRP. • Supports slave mode operation through AHB slave interface. ...
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... NXP Semiconductors 7.7 System functions To enhance the performance of the LPC3220/30/40/50 incorporates the following system functions, an Interrupt Controller (INTC), a watchdog timer, a millisecond timer, and several power control features. These functions are described in the following sections 7.7.1 Interrupt controller The interrupt controller is comprised of three basic interrupt controller blocks, supporting a total of 73 interrupt sources. Each interrupt source can be individually enabled/disabled and confi ...
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... NXP Semiconductors 7.7.4 Clocking and power control features 7.7.4.1 Clocking Clocking in the LPC3220/30/40/50 is designed to be versatile, so that system and peripheral requirements may be met, while allowing optimization of power consumption. Clocks to most functions may be turned off if not needed and some peripherals do this automatically. ...
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... NXP Semiconductors output to be used directly. The maximum PLL output frequency supported by the CPU is 266 MHz. The only output frequency supported by the USB PLL is 48 MHz, and the clock has strict requirements for nominal frequency (500 ppm) and jitter (500 ps). ...
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... NXP Semiconductors 7.8.1 UARTs The LPC3220/30/40/50 contains seven UARTs. Four are standard UARTs, and three are high-speed UARTs. 7.8.1.1 Standard UARTs The four standard UARTs are compatible with the INS16Cx50. These UARTs support rates up to 460800 bit/s from a 13 MHz peripheral clock. ...
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... NXP Semiconductors Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master. The SPI implementation on the LPC3220/30/40/50 does not support operation as a slave. ...
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... NXP Semiconductors There is a separate slave transmit FIFO. The slave transmit FIFO (TXS) and its level are only available when the controller is configured as a Master/Slave device and is operating in a multi-master environment. Separate TX FIFOs are needed in a multi-master because a controller might have a message queued for transmission when an external master addresses come a slave-transmitter, a second source of data is needed ...
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... NXP Semiconductors 7.9 Other peripherals In addition to the communication peripherals there are many general purpose peripherals available in the LPC3220/30/40/50. Here is a list of the general purpose peripherals. • GPI/O • Keyboard scanner • Touch screen controller and 10-bit Analog-to-Digital-Converter • Real-time clock • ...
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... NXP Semiconductors 7.9.2 Keyboard scanner The keyboard scanner function can automatically scan a keyboard keys matrix. In operation, the keyboard scanner’s internal state machine will normally idle state, with all KEY_ROWn pins set high, waiting for a change in the column inputs to indicate that one or more keys have been pressed. ...
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... NXP Semiconductors Two 32-bit match registers are readable and writable by the processor. A match will result in an interrupt provided that the interrupt is enabled. The ONSW output pin can also be triggered by a match event, and cause an external power supply to turn on all of the operating voltages way to startup after power has been removed. ...
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... NXP Semiconductors – set LOW on match – set HIGH on match – toggle on match – do nothing on match 7.9.6 High-speed timer The high-speed timer block is clocked by the main peripheral clock. The clock is first divided down in a 16-bit programmable pre-scale counter which clocks a 32-bit timer/counter ...
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... NXP Semiconductors • 32-bit pulse-width (match) register • 10-bit dead-time register and an associated 10-bit dead-time counter • 32-bit capture register • Two PWM (match) outputs (pins MCOA0/1/2 and MCOB0/1/2) with opposite polarities • Period interrupt, pulse-width interrupt, and capture interrupt 8. Basic architecture The LPC3220/30/40/ general purpose ARM926EJ-S 32-bit microprocessor with instruction cache and data cache ...
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... NXP Semiconductors 9. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (1.2 V) DD(1V2) V external memory controller DD(EMC) supply voltage V analog supply voltage (3.3 V) DDA(3V3) V input/output supply voltage DD(IO) V analog input voltage IA V input voltage ...
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... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter V supply voltage (1.2 V) DD(1V2) V external memory DD(EMC) controller supply voltage V input/output supply DD(IO) voltage V analog supply voltage DDA(3V3) (3.3 V) Run, direct Run, and Stop modes I Run mode supply ...
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... NXP Semiconductors Table 7. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter I LOW-level IL input current I HIGH-level IH input current I I/O latch-up current latch I pull-up current pu I pull-down current pd C input capacitance i Output pins and I/O pins configured as output V output voltage ...
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... NXP Semiconductors Table 7. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter V LOW-level input voltage IL V hysteresis voltage hys I LOW-level IL input current I HIGH-level IH input current I I/O latch-up current latch I pull-up current pu I pull-down current pd C input capacitance i V output voltage ...
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... NXP Semiconductors Table 7. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter pins V input voltage I V HIGH-level IH input voltage V LOW-level IL input voltage I LOW-level IL input current I HIGH-level IH input current I I/O latch-up current latch C input capacitance i V LOW-level OL output voltage I LOW-level OL output current ...
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... NXP Semiconductors Table 7. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter V input voltage I V HIGH-level input voltage 1.2 V inputs IH V LOW-level input voltage IL I LOW-level input current IL I HIGH-level input current OFF-state output OZ current I I/O latch-up current latch [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. ...
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... NXP Semiconductors 10.2 ADC static characteristics Table 8. ADC static characteristics unless otherwise specified; ADC clock frequency 4.5 MHz. DDA(3V3) amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 4. ADC characteristics LPC3220_30_40_50_1 Preliminary data sheet ...
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... NXP Semiconductors 11. Dynamic characteristics 11.1 Clocking and I/O port pins Table 9. Dynamic characteristics +85 C, unless otherwise specified. amb Symbol Parameter Reset t external RESET pulse width w(RESET)ext External clock f external clock frequency ext Port pins t rise time r t fall time f [1] Parameters are valid over operating temperature range unless otherwise specifi ...
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... NXP Semiconductors Table 10. Dynamic characteristics: static external memory interface pF amb DD(EMC) Symbol Parameter t WE LOW to WE HIGH time WELWEH t BLS LOW to BLS HIGH time BLSLBLSH t WE HIGH to address invalid time WEHANV t WE HIGH to data invalid time WEHDNV t BLS HIGH to address invalid time ...
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... NXP Semiconductors EMC_A[23:0] EMC_CS[3:0] EMC_D[31:0] EMC_WR EMC_BLS[3:0] Fig 6. External memory write access LPC3220_30_40_50_1 Preliminary data sheet t CSLAV t CSLDV t WELDV t WEHDNV t CSLWEL t WELWEH t BLSHDNV t CSLBLSL t BLSLBLSH Rev. 01 — 6 February 2009 LPC3220/30/40/50 16/32-bit ARM microcontrollers t WEHANV t BLSHANV 002aae469 © NXP B.V. 2009. All rights reserved. ...
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... NXP Semiconductors 11.3 SDR SDRAM Controller Table 11. EMC SDR SDRAM memory interface dynamic characteristics +85 C, unless otherwise specified. amb Symbol Parameter f operating frequency oper t clock cycle time LOW-level width HIGH-level width CH t control valid delay time d(V)ctrl t control hold time ...
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... NXP Semiconductors Table 12. EMC DDR SDRAM memory interface dynamic characteristics pF amb Symbol Parameter f operating frequency oper t clock cycle time LOW-level width HIGH-level width CH t control valid delay time d(V)ctrl t control hold time h(ctrl) t address valid delay time d(AV) t address hold time ...
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... NXP Semiconductors EMC_CLK EMC control and address signals Fig 8. DDR control timing parameters EMC_CLK command EMC_DQSm EMC_D[31:0], EMC_DQM[1:0] Fig 9. DDR write timing parameters EMC_CLK command EMC_DQSm (1) delayed EMC_DQSm EMC_D[31:0] (1) The delay of the EMC_DQSm signal is determined by the DQS_DELAY settings. See LPC32x0 user manual, External Memory Controller Chapter, section DDR DQS delay calibration for details on confi ...
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... NXP Semiconductors 11.5 Ethernet Table 13. Dynamic characteristics: Ethernet MAC pins Symbol Parameter Ethernet MAC signals for MIIM T clock cycle time cy(clk) t data output valid time v(Q) t data output high-impedance time QZ t data input set-up time su(D) t data input hold time h(D) ...
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... NXP Semiconductors Fig 11. Fig 12. 11.6 USB controller Table 14. Dynamic characteristics USB digital I/O pins +85 C, unless otherwise specified. DD(IO) amb Symbol Parameter t bus turnaround time (I/O) TIO t bus turnaround time (O/I) TOI [1] Parameters are valid over operating temperature range unless otherwise specified. ...
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... NXP Semiconductors Fig 13. USB bus turnaround time 11.7 Secure Digital (SD) card interface Table 15. Dynamic characteristics: SD card pin interface +85 C for industrial applications; V amb Symbol Parameter T clock cycle time cy(clk) t data input set-up time su(D) t data input hold time h(D) t data output valid delay time ...
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... NXP Semiconductors 11.8 MLC NAND flash memory controller Table 16. Dynamic characteristics of the MLC NAND flash memory controller +85 C. amb Symbol Parameter t CE LOW to RE LOW time CELREL t RE cycle time HIGH hold time REH t RE HIGH to output high-impedance time RHZ t RE pulse width ...
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... NXP Semiconductors Fig 16. 11.9 SLC NAND flash memory controller Table 17. Dynamic characteristics of SLC NAND flash memory controller +85 C. amb Symbol Parameter t ALE set-up time ALS t ALE hold time ALH t ALE to RE delay time access time CEA t CE set-up time hold time ...
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... NXP Semiconductors Table 17. Dynamic characteristics of SLC NAND flash memory controller +85 C. amb Symbol Parameter t data set-up time DS t output high-impedance LOW time t RE cycle time access time REA t RE high hold time REH t RE HIGH to output hold time RHOH t RE HIGH to output ...
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... NXP Semiconductors FLASH_CE t t CLS CLH FLASH_CLE t WP FLASH_WR t t ALS ALH FLASH_ALE command FLASH_IO[7:0] FLASH_RDY t WB command Fig 17. MLC NAND flash memory write timing (writing to NAND flash) LPC3220_30_40_50_1 Preliminary data sheet LPC3220/30/40/ CLS ALS ALH ALS address address Rev. 01 — 6 February 2009 ...
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... NXP Semiconductors t t ALS ALH FLASH_ALE t t CLS CLH FLASH_CLE FLASH_RDY FLASH_WR FLASH_RD command FLASH_IO[7: FLASH_CE command Fig 18. MLC NAND Flash memory read timing (reading from NAND flash) LPC3220_30_40_50_1 Preliminary data sheet t t ALS ALH t CLS CLR address CEA address Rev. 01 — 6 February 2009 ...
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... NXP Semiconductors t CS FLASH_CE t CLS FLASH_CLE t WP FLASH_WR FLASH_RD FLASH_IO[7:0] Fig 19. MLC NAND flash memory status timing 11.10 SPI and SSP Controller 11.10.1 SPI Table 18. Dynamic characteristics of SPI pins on SPI master controller +85 C. amb Symbol Parameter Common to SPI1 and SPI2 T SPI cycle time ...
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... NXP Semiconductors 11.10.2 SSP Table 19. Dynamic characteristics of SSP controller pins in SPI mode +85 C. amb Symbol Parameter SSP 0 in SPI master mode T SPI cycle time SPICYC t SPICLK HIGH time SPICLKH t SPICLK LOW time SPICLKL t SPI data set-up time SPIDSU t SPI data hold time ...
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... NXP Semiconductors 11.10.3 Timing diagrams for SPI and SSP (in SPI mode) Fig 20. Fig 21. LPC3220_30_40_50_1 Preliminary data sheet SPI1/2_CLK or SCK0/1 (CPOL = 0) SPI1/2_CLK or SCK0/1 (CPOL = 1) t SPIQV SPI1/2_DATAIO or DATA VALID MOSI0/1 SPI1/2_DATAIN or DATA VALID MISO0/1 SPI master timing (CPHA = 0) T SPICYC SPI1/2_CLK or SCK0/1 (CPOL = 0) ...
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... NXP Semiconductors Fig 22. Fig 23. LPC3220_30_40_50_1 Preliminary data sheet SPI1/2_CLK or SCK0/1 (CPOL = 0) SPI1/2_CLK or SCK0/1 (CPOL = 1) SPI1/2_DATAIO or DATA VALID MOSI0/1 t SPIQV SPI1/2_DATAIN or DATA VALID MISO0/1 SPI slave timing (CPHA = 0) T SPICYC SPI1/2_CLK or SCK0/1 (CPOL = 0) SPI1/2_CLK or SCK0/1 (CPOL = 1) SPI1/2_DATAIO or DATA VALID MOSI0/1 SPI1/2_DATAIN or DATA VALID ...
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... NXP Semiconductors 12. Package outline TFBGA296: plastic thin fine-pitch ball grid array package; 296 balls ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 0.80 0.5 mm 1.2 0.3 0.65 0.4 OUTLINE VERSION IEC SOT1048-1 Fig 24. Package outline SOT1048-1 (TFBGA296) ...
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... NXP Semiconductors 13. Abbreviations Table 20. Acronym ADC AHB AMBA APB CISC DDR SDRAM DMA DSP ETM FAB FIFO FIQ GPIO I/O IRQ HS IrDA JTAG LCD MAC MIIM OHCI OTG PHY PLL PWM RAM RMII SE0 SDR SDRAM SPI SSI SSP TFT TTL ...
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... NXP Semiconductors 14. Revision history Table 21. Revision history Document ID Release date LPC3220_30_40_50_1 20090206 LPC3220_30_40_50_1 Preliminary data sheet Data sheet status Change notice Preliminary data sheet - Rev. 01 — 6 February 2009 LPC3220/30/40/50 16/32-bit ARM microcontrollers Supersedes - © NXP B.V. 2009. All rights reserved ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Functional description . . . . . . . . . . . . . . . . . . 21 7.1 CPU and subsystems . . . . . . . . . . . . . . . . . . . 21 7.1.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1.2 Vector Floating Point (VFP) coprocessor . . . . 21 7 ...
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... NXP Semiconductors 11.4 DDR SDRAM controller . . . . . . . . . . . . . . . . . 53 11.5 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.6 USB controller 11.7 Secure Digital (SD) card interface . . . . . . . . . 58 11.8 MLC NAND flash memory controller . . . . . . . 59 11.9 SLC NAND flash memory controller . . . . . . . . 60 11.10 SPI and SSP Controller . . . . . . . . . . . . . . . . . 64 11.10.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.10.2 SSP 11.10.3 Timing diagrams for SPI and SSP (in SPI mode) ...