LPC2388FBD144,551 NXP Semiconductors, LPC2388FBD144,551 Datasheet
LPC2388FBD144,551
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LPC2388FBD144-S
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LPC2388 Single-chip 16-bit/32-bit microcontroller; 512 kB flash with ISP/IAP, Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC Rev. 00.01 — 23 October 2007 1. General description The LPC2388 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that ...
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... NXP Semiconductors General Purpose AHB DMA controller (GPDMA) that can be used with the SSP serial interfaces, the I as well as for memory-to-memory transfers. Serial Interfaces: Ethernet MAC with associated DMA controller. These functions reside on an independent AHB bus. USB 2.0 device/host/OTG with on-chip PHY and associated DMA controller. ...
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... NXP Semiconductors 4 MHz internal RC oscillator trimmed accuracy that can optionally be used as the system clock. When used as the CPU clock, does not allow CAN and USB to run. On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator ...
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... NXP Semiconductors 5. Block diagram LPC2388 P0, P1, P2 P3, P4 SRAM HIGH-SPEED GPI/O CONTROLLERS 104 PINS TOTAL SRAM AHB2 ETHERNET 16 kB RMII(8) MAC WITH SRAM DMA EINT3 to EINT0 EXTERNAL INTERRUPTS P0 × CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 × MAT2, TIMER2/TIMER3 2 × MAT0/MAT1/ MAT3 6 × PWM1 PWM1 2 × ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. LPC2388 pinning 6.2 Pin description Table 3. Pin description Symbol Pin Type P0[0] to P0[31] I/O [1] P0[0]/RD1/TXD/ 66 I/O SDA1 I O I/O [1] P0[1]/TD1/RXD3/ 67 I/O SCL1 O I I/O [1] P0[2]/TXD0 141 I/O O [1] P0[3]/RXD0 142 ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P0[5]/ 115 I/O I2SRX_WS/ I/O TD2/CAP2[ [1] P0[6]/ 113 I/O I2SRX_SDA/ I/O SSEL1/MAT2[0] I/O O [1] P0[7]/ 112 I/O I2STX_CLK/ I/O SCK1/MAT2[1] I/O O [1] P0[8]/ 111 I/O I2STX_WS/ I/O MISO1/MAT2[2] I/O O [1] P0[9]/ 109 ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P0[14]/ 48 I/O USB_HSTEN2/ O USB_CONNECT2/ O SSEL1 I/O [1] P0[15]/TXD1/ 89 I/O SCK0/SCK O I/O I/O [1] P0[16]/RXD1/ 90 I/O SSEL0/SSEL I I/O I/O [1] P0[17]/CTS1/ 87 I/O MISO0/MISO I I/O I/O [1] P0[18]/DCD1/ 86 I/O MOSI0/MOSI I I/O I/O [1] P0[19]/DSR1/ ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [2] P0[23]/AD0[0]/ 13 I/O I2SRX_CLK/ I CAP3[0] I/O I [3] P0[24]/AD0[1]/ 11 I/O I2SRX_WS/ I CAP3[1] I/O I [2] P0[25]/AD0[2]/ 10 I/O I2SRX_SDA/ I TXD3 I/O O [2] P0[26]/AD0[3]/ 8 I/O AOUT/RXD3 [4] P0[27]/SDA0 35 I/O I/O [4] P0[28]/SCL0 34 I/O ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P1[10]/ 129 I/O ENET_RXD1 I [1] P1[14]/ 128 I/O ENET_RX_ER I [1] P1[15]/ 126 I/O ENET_REF_CLK I [1] P1[16]/ 125 I/O ENET_MDC O [1] P1[17]/ 123 I/O ENET_MDIO I/O [1] P1[18]/ 46 I/O USB_UP_LED1/ O PWM1[1]/ CAP1[ [1] P1[19]/ 47 I/O ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P1[25]/ 56 I/O USB_LS1/ O USB_HSTEN1/ O MAT1[1] O [1] P1[26]/ 57 I/O USB_SSPND1/ O PWM1[6]/ O CAP0[0] I [1] P1[27]/ 61 I/O USB_INT1/ I USB_OVRCR1/ I CAP0[1] I [1] P1[28]/ 63 I/O USB_SCL1/ I/O PCAP1[0]/ I MAT0[0] O [1] P1[29]/ 64 I/O USB_SDA1/ I/O PCAP1[1]/ I MAT0[1] O [2] ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P2[2]/PWM1[3]/ 105 I/O CTS1/ O PIPESTAT1 I O [1] P2[3]/PWM1[4]/ 100 I/O DCD1/ O PIPESTAT2 I O [1] P2[4]/PWM1[5]/ 99 I/O DSR1/ O TRACESYNC I O [1] P2[5]/PWM1[6]/ 97 I/O DTR1/ O TRACEPKT0 O O [1] P2[6]/PCAP1[0]/ 96 I/O RI1/ I TRACEPKT1 I O [1] ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [6] P2[11]/EINT1/ 75 I/O MCIDAT1/ I I2STX_CLK O I/O [6] P2[12]/EINT2/ 73 I/O MCIDAT2/ I I2STX_WS O I/O [6] P2[13]/EINT3/ 71 I/O MCIDAT3/ I I2STX_SDA O I/O P3[0] to P3[31] I/O [1] P3[0]/D0 137 I/O I/O [1] P3[1]/D1 140 I/O I/O [1] P3[2]/D2 144 I/O ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P3[25]/MAT0[0]/ 39 I/O PWM1[ [1] P3[26]/MAT0[1]/ 38 I/O PWM1[ P4[0] to P4[31] I/O [1] P4[0]/A0 52 I/O I/O [1] P4[1]/A1 55 I/O I/O [1] P4[2]/A2 58 I/O I/O [1] P4[3]/A3 68 I/O I/O [1] P4[4]/A4 72 I/O I/O [1] P4[5]/A5 ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P4[24]/OE 127 I/O O [1] P4[25]/BLS0 124 I/O O [1] P4[28]/MAT2[0]/ 118 I/O TXD3 O O [1] P4[29]/MAT2[1]/ 122 I/O RXD3 O I [1] P4[30]/CS0 130 I/O O [1] P4[31]/CS1 134 I/O O [8] ALARM ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type V 41, 62, I DD(3V3) 77, 102, 114, [11] 138 n.c. 21, 81, I [12 18, 60, I DD(DCDC)(3V3) [13] 121 [14 DDA [14] VREF 17 I [14] VBAT tolerant pad providing digital I/O functions with TTL levels and hysteresis. [ tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a DAC input, digital section of the pad is disabled ...
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... NXP Semiconductors The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1. ...
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... NXP Semiconductors The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to allow it to operate at SRAM speeds of 72 MHz. The LPC2388 provides a minimum of 100 000 write/erase cycles and 20 years of data retention. 7.3 On-chip SRAM The LPC2388 includes a SRAM memory reserved for the ARM processor exclusive use ...
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... NXP Semiconductors 4.0 GB 3.75 GB 3.5 GB 3.0 GB 2.0 GB 1.0 GB 0.0 GB Fig 3. LPC2388 memory map 7.5 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types ...
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... NXP Semiconductors FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device ...
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... NXP Semiconductors • Static memory features include: – Asynchronous page mode read – Programmable Wait States (WST) – Bus turnaround delay – Output enable and write enable delays – Extended wait 7.8 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2388 peripherals to have DMA support ...
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... NXP Semiconductors • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Interrupt masking. The DMA error and DMA terminal count interrupt requests can be masked. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking ...
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... NXP Semiconductors via the EMC, as well as the SRAM located on another AHB not being used by the USB block. However, using memory other than the Ethernet SRAM, especially off-chip memory, will slow Ethernet access to memory and increase the loading of its AHB. The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus ...
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... NXP Semiconductors 7.11 USB interface The Universal Serial Bus (USB 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The Host Controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the Host Controller ...
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... NXP Semiconductors 7.11.3 USB OTG Controller USB OTG (On-The-Go supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the Host Controller, device controller, and a master-only ...
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... NXP Semiconductors 7.13 10-bit ADC The LPC2388 contains one ADC single 10-bit successive approximation ADC with eight channels. 7.13.1 Features • 10-bit successive approximation ADC • Input multiplexing among 8 pins • Power-down mode • Measurement range 10-bit conversion time ≥ 2.44 μs • ...
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... NXP Semiconductors • UART3 includes an IrDA mode to support infrared communication. 7.16 SPI serial I/O controller The LPC2388 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer ...
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... NXP Semiconductors • Can be used as a multimedia card bus or a secure digital memory card bus host. The SD/MMC can be connected to several multimedia cards or a single secure digital memory card. • DMA supported through the GPDMA controller. 2 7.19 I C-bus serial I/O controllers ...
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... NXP Semiconductors • Mono and stereo audio data supported. • The sampling frequency can range from 16 kHz to 48 kHz ((16, 22.05, 32, 44.1, 48) kHz). • Configurable word select period in master mode (separately for I • Two 8 word FIFO data buffers are provided, one for transmit and one for receive. ...
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... NXP Semiconductors The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match ...
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... NXP Semiconductors 7.23 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time. ...
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... NXP Semiconductors • An alarm output pin is included to assist in waking up from Power-down mode, or when the chip has had power removed to all functions except the RTC and Battery RAM. • Periodic interrupts can be generated from increments of any field of the time registers, and selected fractional second values. ...
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... NXP Semiconductors Following the PLL input divider is the PLL multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO value ‘M’, in the range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to 550 MHz ...
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... NXP Semiconductors 7.25.4.1 Idle mode In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses ...
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... NXP Semiconductors The first option assumes that power consumption is not a concern and the design ties the V and V DD(3V3) supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive. The second option uses two power supplies ...
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... NXP Semiconductors 7.26.3 Code security (Code Read Protection - CRP) This feature of the LPC2388 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. ...
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... NXP Semiconductors 7.27 Emulation and debugging The LPC2388 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface peripherals residing on other pins are available during the development and debugging phase as they are when the application is run in the embedded system itself ...
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... NXP Semiconductors 7.27.3 RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2388 contain a specific configuration of RealMonitor software programmed into the on-chip ROM memory ...
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... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter supply voltage DD(DCDC)(3V3) (3 analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V input voltage on pin VREF ...
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... NXP Semiconductors 9. Static characteristics Table 5. Static characteristics − ° ° +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter DD(DCDC)(3V3) supply voltage (3 analog 3.3 V pad DDA supply voltage V input voltage on pin i(VBAT) VBAT ...
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... NXP Semiconductors Table 5. Static characteristics …continued − ° ° +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter I active mode DC-to-DC DD(DCDC)act(3V3) converter supply current (3 power-down mode DD(DCDC)pd(3V3) DC-to-DC converter supply current (3 active mode battery BATact supply current 2 I C-bus pins (P0[27] and P0[28]) ...
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... NXP Semiconductors Table 5. Static characteristics …continued − ° ° +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V differential input DI sensitivity V differential common CM mode voltage range V single-ended receiver th(rs)se switching threshold voltage V LOW-level output OL voltage for low-/full-speed V HIGH-level output ...
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... NXP Semiconductors [1] Conditions 3.3 V. SSA DDA [2] The ADC is monotonic, there are no missing codes. [3] The differential linearity error ( the difference between the actual step width and the ideal step width. See D [4] The integral non-linearity ( the peak difference between the center of the steps of the actual and the ideal transfer curve after L(adj) appropriate adjustment of gain and offset errors ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 4. ADC characteristics LPC2388_0 Preliminary data sheet ...
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... NXP Semiconductors AD0[y] SAMPLE Fig 5. Suggested ADC interface - LPC2388 AD0[y] pin LPC2388_0 Preliminary data sheet LPC2378 R vsi 20 kΩ AD0[ Rev. 00.01 — 23 October 2007 LPC2388 Fast communication chip V EXT 002aac610 © NXP B.V. 2007. All rights reserved ...
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... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics of USB pins (full-speed) Ω pF 1 Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT t source jitter for differential transition ...
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... NXP Semiconductors 10.1 Timing − 0 0.2V 0. Fig 6. External clock timing t PERIOD crossover point differential data lines differential data to n × t Fig 7. Differential data-to-EOP transition skew and EOP width shifting edges SCK MOSI MISO Fig 8. MISO line set-up time in SSP Master mode ...
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... NXP Semiconductors 11. Application information 11.1 Suggested USB interface solutions LPC23XX Fig 9. LPC2388 USB interface on a self-powered device LPC23XX Fig 10. LPC2388 USB interface on a bus-powered device LPC2388_0 Preliminary data sheet V DD(3V3) USB_UP_LED USB_CONNECT soft-connect switch R1 1.5 kΩ V BUS Ω USB_D Ω USB_D− ...
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... NXP Semiconductors RSTOUT USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D−1 USB_UP_LED1 LPC2388 USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 11. LPC2388 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2388_0 Preliminary data sheet RESET_N ADR/PSW OE_N/INT_N V DD SPEED ...
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... NXP Semiconductors RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 LPC2388 USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1 Fig 12. LPC2388 USB OTG port configuration: VP_VM mode LPC2388_0 Preliminary data sheet V DD RESET_N OE_N/INT_N DAT_VP SE0_VM RCV ISP1301 ADR/PSW SPEED SUSPEND SCL SDA INT_N V DD Rev. 00.01 — 23 October 2007 ...
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... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC2388 USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D−2 V BUS Fig 13. LPC2388 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2388_0 Preliminary data sheet Ω 33 Ω 15 kΩ 15 kΩ FLAGA ENA OUTA ...
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... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC2388 USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 14. LPC2388 USB OTG port configuration: USB port 1 host, USB port 2 host LPC2388_0 Preliminary data sheet Ω 33 Ω 15 kΩ 15 kΩ FLAGA ENA ...
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... NXP Semiconductors 12. Package outline LQFP144: plastic low profile quad flat package; 144 leads; body 1 108 109 pin 1 index 144 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Abbreviations Table 9. Acronym ADC AHB AMBA APB BLS BOD CAN CTS DAC DCC DMA DSP EOP ETM GPIO IrDA JTAG MII PHY PLL PWM RMII RTS SE0 SPI SSI SSP TTL UART USB LPC2388_0 Preliminary data sheet Acronym list ...
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... NXP Semiconductors 14. Revision history Table 10. Revision history Document ID Release date LPC2388_0.01 <tbd> LPC2388_0 Preliminary data sheet Data sheet status Change notice Rev. 00.01 — 23 October 2007 LPC2388 Fast communication chip Supersedes © NXP B.V. 2007. All rights reserved ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . 15 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 15 7.2 On-chip flash programming memory . . . . . . . 16 7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 17 7.4 Memory map ...
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... NXP Semiconductors 15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 15.4 Trademarks Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Fast communication chip Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp ...